Question about programming in VHDL.

[hassan590]

I am a beginner in vhdl. i just learned how do we program in vhdl. i was trying to make a program which has two entities as counters i declared an array and different values are placed at each location in that array. the counter has to pick a value from each location and decrements it down to zero i want both counters to pick values from the same array in such away that 1st counter picks value from 1st location and 2nd counter from second counter picks from second location the one who decrements to zero first, picks the value from next location. My supervisor gave me this task to understand how to entities interact with each other. I need some help to complete that task. i have written code for one counter which is decrementing the values after picking them from array and i have no idea how 2nd counter would be working with counter 1 to perform the actual task which is mentioned above.what should i be doing? i hope u people would help me.

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Code VHDL - [expand]
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library IEEE;
 use IEEE.std_logic_1164.all; 
 use IEEE.std_logic_unsigned.all 
 use ieee.numeric_std.all;
 
entity counter is
port(clk,reset :in std_logic;
     type my_array is array(1 to 8) of integer;  
     total:out unsigned(3 downto 0);
     constant set:my_array:= (2,4,6,8,10,12,14,16));
 
architecture imp of counter is
 
signal count:unsigned(3 downto 0);
variable i : integer RANGE 0 TO 8 := 0; 
variable t : integer:=0
begin
process(clk);
count=set(i+1)
if rising_edge(Clk) then
if (count>0) then
count<=count-1;
t<=t+1
else
i:=i+1;
end if;
end if;
end process;
total=t;
end imp;

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[ads-ee]

First of all VHDL is not a programming language, so don't try writing SW programs with VHDL.

VHDL is a hardware description language. So think of what the hardware that is required to do what you want. Your drawing doesn't show how the HW would function. You would need a multiplexer on the input of each counter so you can load different array addresses into the counters. The mux for counter 1 will require a select that is also used as the array address select but appended with 0 and counter 2 will require another address select that is appended with 1 to form the array address. The line between counters doesn't seem to make sense. Interactions between counters can be reduce to one clock if there are independent address generators for each counter and an arbiter between counters accesses. Or use a dual port memory and you can have both counters access different addresses as the same time. I'll let you figure out the reset.

Oh, yeah. Get rid of the variables, you can uses them after you can code everything without them. As a HW guy I've never used variables except in very specific cases where it improves the readability of the code. SW types always want to use variables in VHDL to excess, much to their detriment.

regards

 

[hassan590]

how should i be using a mux with counter..can i get an example from you?

 

[TrickyDicky]

muxes and counters are very basic hardware concepts. You should look them up yourself.

 

[ads-ee]

Well I was using your drawing as the basis. You don't necessarily need a mux if there is a memory in place of the array and not just a bunch of registers holding the values. The mux will allow you to select the register you want to access in your "array" of registers. From a SW perspective think case statement when thinking of a HW mux (some select chooses between inputs (cases) to generate an output).

What I don't understand is why would your supervisor (I'm assuming this is a job) want a SW engineer working on VHDL? Last place I worked where they gave the SW engineers the job of designing and taping out a bunch of ASICs written in VHDL (Upper level management says. It looks just like SW. Besides those ASIC guys we tried to hire were asking for too much money)...none of the ASICs worked and the designs had very large numbers of logic levels between registers, if they had any registers. Needless to say they hired HW engineers with ASIC backgrounds (getting paid a lot of $) to clean up the mess.

Before anyone can say SW engineers can learn how to correctly "program" in VHDL. I agree they can, if they learn to think of parallel sequential logic and design their VHDL/Verilog code with that in mind.