mpefareo
Newbie level 3
What I was going to do in VHDL is to define a pointer to array, later dereference that pointer to a particular index and assign it to approp variable
I have got this code: The idea is to assign pointer to array of sg_list_t to sg_list_t variable:
I have compiled the code with ISIM Xilinx simulator but it complains about v_sg_list := pdma(id).p_a_sg_list.all(i);
There is a way to go around ISIM compilation problem:
But I don't like this solution.
Has anybody got any ideas of how to sort it?
I'm not sure if it my code or simulator problem ISIM is a bit strange in some cases. I have not tried to use any simulator. Haven't got any
The information in books about VHDL pointers is not good. I could find any examples of similar code in net either.
Has anybody got any ideas is it the code problem, may be it is not posible to do this sort of things in VHDL?
Thank you in advance.
I have got this code: The idea is to assign pointer to array of sg_list_t to sg_list_t variable:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 type sg_list_t is record va : natural; -- address of buffer, not index in sys_mem len : natural; -- length of buffer end record; type a_sg_list_t is array(natural range <>) of sg_list_t; type p_a_sg_list_t is access a_sg_list_t; -- Later in function, I have got procedure dma_unmap( dprop : in dma_prop_t ) is alias id : natural is dprop.id; variable v_sg_list : sg_list_t; -- this is a variable I was going to assign dereferenced pointer to array begin for i in 0 to pdma(id).sg_table.sg_len - 1 loop v_sg_list := pdma(id).p_a_sg_list.all(i); -- this is the problematic line!!!!!!!!!!!!!!!!!!!!!!!!! rm_dma_free(v_sg_list.va); end loop; rm_table_free(pdma(id).sg_table.sgd_va); deallocate(pdma(id).p_a_sg_list); pdma(id).dma_state := DMA_OPEN_ST; end dma_unmap;
I have compiled the code with ISIM Xilinx simulator but it complains about v_sg_list := pdma(id).p_a_sg_list.all(i);
There is a way to go around ISIM compilation problem:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 procedure dma_unmap( dprop : in dma_prop_t ) is alias id : natural is dprop.id; variable v_a_sg_list : a_sg_list_t(0 to dprop.sg_len - 1); begin v_a_sg_list := pdma(id).p_a_sg_list.all; for i in 0 to pdma(id).sg_table.sg_len - 1 loop rm_dma_free(v_a_sg_list(i).va); end loop; -- rm_table_free(pdma(id).sg_table.sgd_va); -- deallocate(pdma(id).p_a_sg_list); -- pdma(id).dma_state := DMA_OPEN_ST; end dma_unmap;
But I don't like this solution.
Has anybody got any ideas of how to sort it?
I'm not sure if it my code or simulator problem ISIM is a bit strange in some cases. I have not tried to use any simulator. Haven't got any
The information in books about VHDL pointers is not good. I could find any examples of similar code in net either.
Has anybody got any ideas is it the code problem, may be it is not posible to do this sort of things in VHDL?
Thank you in advance.
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