Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question about pnoise simulation in cadence:

Status
Not open for further replies.

mohamedabouzied

Member level 3
Joined
Feb 19, 2006
Messages
60
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,721
cadence pnoise simulation

Hello all
When i do pnoise of a charge pump of a pll,

the output is dBc/Hz
so, it is normalized to the carrier, right?
What is the carrier here?

i understand this simulation for oscillators as there is a sinsoid carrier i normalized w.r.t. it but for charge pump what is the carrier???????

MohamedAbouzied
 

hello safwat,
i also gussed this but the carrier is voltage or current??

it seems to be current, am i right??
 

ok, let me tell u what i can remember, u should measure the current noise of the CP then multiply it by some factor alpha representing the period that the CP will be ON during lock, then multiply the result current noise by the Transfer function of the current to the output phase, then u calculate the phase noise from L(fm)=theta^2(fm)/2.
that is what i could remember :(
a good paper to refer to is: https://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top