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question about metal filling

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field_catcher

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Hello All,

After we finish the layout, metal filling is used to meet the density requirement. Do we tie the metal filling to ground or let it floating ? which one is better?


Thanks!
 

Usialu you have to do filling for each metal layer. If I have chance to place big areas of metal atop each other I usualy try to connect them to VCC / VEE just to have some more bypass cap.
For anything else I let it float.
 

You should use dummy metal filling until you get a density of > 25% - a requirement for the metal etch processes in the fab. The dummy metal need not be connected to anything but do not place dummy metal over critical analogue cricuitry or any matched components (eg current mirrors etc)
 

Colbhaidh said:
You should use dummy metal filling until you get a density of > 25% - a requirement for the metal etch processes in the fab. The dummy metal need not be connected to anything but do not place dummy metal over critical analogue cricuitry or any matched components (eg current mirrors etc)
Click to expand...

Anyway, Instead of just let it floating, can we biasing the metal filing with fixed bias voltage (e.g. VDD or GND) since this is quite useful and efficient to have such metal filing as extra decoupling capacitance.
 

Hi,

Just for sharing. In my experience, there have been reports of damages on IC for large floating metal dummies. Most of them caused by discharging of static charges on these metals during CMP process. Through microscope, it was seen clearly a big "bomb" (i.e. burnt marks) was shown on certain ICs with large floating metal.

My recommendation is to keep it grounded if not too painful to do so.
 

All dummy metal should be connected to some fix potential. For example: in TSMC 0.13um gives errors if you left some fil metal floating, also they provide special metal layers just for filling that have different rules from normal metal.

Hope this helps.

Bastos
 

Hello All:
If the metal filling is connect to ground, as the result, it will raise the capacitance between ground and critical node, ex: high bandwidth circuit, filter, etc..... .
It will produce a difference between presim and postsim. Unless, the metal filling paracitic capacitance is including considering.
 

wee_liang said:
Hi,

Just for sharing. In my experience, there have been reports of damages on IC for large floating metal dummies. Most of them caused by discharging of static charges on these metals during CMP process. Through microscope, it was seen clearly a big "bomb" (i.e. burnt marks) was shown on certain ICs with large floating metal.

My recommendation is to keep it grounded if not too painful to do so.
Click to expand...

But during the fab process, although you bias it in fixed potential, they are still floating in the fab process since your circuits is not working in the fab nor you have any supply on it. How can I protect such metal filing ?
 

Hi terryssw,

I think the point of wee_liang is if you tie the dummy metal filling to gnd/vcc,the static charges accumulated during CMP will go away once put into work;otherwise the accumulated static charges may affect the reliability or even damage your IC.

hope it helps.

regards,
jordan76
 

But isn't that the static charge is discharge away thorugh the outside pin connected to VDD or gnd, while during the fab process this pins is still floating? Also, will the accumlated static charge damaged immediately the IC before the end of the fabrication?
 

CMP cannot itself cause any damage. This process leaves about 1um of more of TEOS above any metal lines. Any damage must have come from an ESD event where metal is exposed at the surface of the chip (metal etch etc) or after completion during assembly or something.
During Fab processing, if the metal lines are connected to any substrate diode (eg N+ or P+) then electrostatic static charges that may be evident during processing will be connected to the wafer substrate through the relevant diodes. This means there is no potyential between the metal and the substrate so no damage.
However, even leaving them floating, modern processing does not leave residual charge on the surface (or should not). Also, dummy lines should be placed over field isolated areas so if there was any charge, it could not damage anything.
 

In 'the art of analog layout",the dummy resistor is tied to the most negative voltage.I think the metal is also tied to the negative .
 

Colbhaidh said:
CMP cannot itself cause any damage. This process leaves about 1um of more of TEOS above any metal lines. Any damage must have come from an ESD event where metal is exposed at the surface of the chip (metal etch etc) or after completion during assembly or something.
During Fab processing, if the metal lines are connected to any substrate diode (eg N+ or P+) then electrostatic static charges that may be evident during processing will be connected to the wafer substrate through the relevant diodes. This means there is no potyential between the metal and the substrate so no damage.
However, even leaving them floating, modern processing does not leave residual charge on the surface (or should not). Also, dummy lines should be placed over field isolated areas so if there was any charge, it could not damage anything.
Click to expand...

So, what is the most suitable treatment of such dummy metal line? Let it floating, connect it to fixed bias voltage or connected it to a p-n junction (diode or substrate), and don't let it cover any of the active area (MOSFET)?
 

Thanks to others for clarifying my comments previously.

My recommendation is as such:

If metal dummies are huge (e.g. 100um x 100um or more), it's recommended to tie it to ground potential.

If metal dummies are smaller, it should be OK to keep them floating.
 

all layers and all part in ic layout must be connected to some potential. It's bad to have floating metal or well or any other component everithing must be connected.
 

It surely depends on Design rules of the fab but usually you can leave the dummy metals floating.
For large metals as mentioned above there should be "Antenna rules" which cover this issue. Then you have to connect them to diffusion.

In case you connect dummy metal to any potential it would be goodidea to leave a bigger gap between those and signal lines.
If you connect them you can use those dummy metals as additional decoupling cap - ie M2-VEE M3-VDD - it is not big cap but every fF counts....
 

does anyone know or have a "free" tool that can do this job?
 

Calibre can do that quite well!
 

actually i meant something like a SKILL program that can handle this, 'coz we only have a complete Cadence package...
 

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