question about memory and data

[mersault]

Hello,
I made a project with that will save some data in a memory generated with the core generator ( a single port memory). Once I finished to do the process , that's turn on the fpga, download the .bit file, press one button to start and wait until it ends, how can I read the data stored in the memory?.. but not reading using HDL, I mean, open a file in Windows and see what's inside the memory. there's a way to do what I say in the last line?

I have a Spartan 3e.

Thank you !.

Greetings

 

[microKernel]

If you have generated only the memory and not the memory controller then you'll need to do that.

Once you interface your memory with the memory controller (either in FPGA) or a separate one, you can write a driver for the memory controller to read/write to the memory.

 

[Maxwell077]

There is a perfect way of observing inside the FPGA.
It is Chipscope Pro, Xilinx tool and can only be used at Xilinx FPGA.
Great tool for debugging, and can be used as a chip-inside osciloscope.

You can add a CS file to your project and do some configs.
You can observe any signals and all of your data coming through or going from to your RAM from CS.

Good luck...
Ilgaz

 

[mersault]

thank you for the answers !!..
but.. in the time after the answers I made a rs232 controller and read the data stored in the memory so, now I can see it with Hyperterminal

that was a simple solution ...

 

[Maxwell077]

Good way, good luck.
Keep CS in your mind

 

[xtcx]

Well! chipscope captures a maximum of 16000 samples...in one time and at many times its not synchronous or not capturing all instances....Good tool but it's hard to capture unperiodic behavior of a signal or register....IS it possible so?.

 

[Maxwell077]

I don't know that you know how to use ChipScope well..
The sampling depends on how many BRAM's you have in your device and how many signals you added to your CS project.
CS puts BRAM's in front of the signals you added and saves the values, and shows them to you from GUI.
If you want more samples, CS need more BRAM's, and if there isn't enough BRAM, you can't get more samples.
Try to get your unnecessary signals from your project...

You can be synchronous to your trigger signal(s). Find a trigger port which means CS shows you the values of signals you added when trigger occurs...
There are some options in CS you need to know, I hope you know them

I think you need more than one trigger port to observe unperiodic signals.
I hope it helps.. Give more detail what you're observing and when you want to do..
May be I can help you more...

Good luck
Ilgaz