Having frequency and phase lock-loops with different transfer characteristic can make sense to improve the lock behavior. Building it with two charge pumps is just an implementation detail that shouldn't be overrated. Presume you know what's the difference between frequency and phase detector and what's their purpose in a PLL.
Without guessing too much, you can assume that both charge pumps are activated mutual exclusively, the frequency detector signal is only active in unlocked state and the phase detector in locked state. A standard PLL with combined phase/frequency detector can be expected to activate the charge pump up/down outputs in unlocked state with 100 % duty cycle. The present design does the same, but has the option to tune the frequency detector transfer characteristic differently.
To find the transfer characteristic, you need the quantitative parameters of all blocks and components.