Question about layout / placement of crystal

[parra]

Hi,

I've got a question about the attached picture: Is this good PCB layout?

Some more infos: A two layer board is used. The top layer is a ground plane, routing is made on the bottom layer. A through-hole-IC is placed on the top layer. Between the IC's pins on the bottom layer, there is a SMD-crystal (+ SMD load capacitances).

Is it a good idea to place the crystal this way, and what could I do to reduce the clock feedtrough?

 

[cyberrat]

Are the actual clock pins on opposite sides of the IC?
Weird.

The thin track from the end pin, I'd take that so it enters the Xtal pad at the corner rather than makes the acid trap where it is.

 

[JAY-R]

This is definely a very bad placement image!!

Crosstalk!!

 

[parra]

Are the actual clock pins on opposite sides of the IC?
Weird.

The thin track from the end pin, I'd take that so it enters the Xtal pad at the corner rather than makes the acid trap where it is.

Well, it's a through-hole-IC. The IC is on the top layer, but it's pins are soldered on the bottom layer. The crystal is a SMD-one, so it is also soldered on the bottom layer. So, in the end, there is a ground plane between the IC and the crystal.

This is definely a very bad placement image!!

Crosstalk!!

How to do it better then?

 

[Frosty]

Is it not an option to use a SMT Oscillator instead?

I assume the bottom 2 pins on right is the IC OSC pins and the tap on the xtal going to the upper row pins is designed for some other purpose.

Optimise your layout around the OSC pins first then route from the XO pin to wherever you are going with the clock using some series termination. But using a tap from the OSC pins is not really a good idea, they way you have done it anyway as the influence on the OSC pins will be quite drastic. Especially if the xtal is pulled. It creates more issues than it will solve.

Otherwise, use a xtal osc instead of the xtal, then use a single gate logice device to buffer the clock signal to your second termination point

:F

 

[parra]

The way the pins are connected is how it's explained in the datasheet (see attached picture)

The two bottom pins are the two clock inputs. The pin in the upper row is OSC Out. In the datasheet it's written, that the crystal has to be connected to CLK A on one side, and connected to CLK B and OSC Out on the other side. So all the connections have to be done this way and it's only a placement / routing issue where I'm not sure how to improve it.

 

[FvM]

There have been many consideration about possible problem. Unfortunately, the oscillator frequency hasn't been mentioned at all, nor if any nets are particularly susceptible for cross-talk, feedthrough, whatever.

Without these informations, I don't see a reason to assume any of the said problems so far.