question about how to use "`include" in verilog

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I download uart16550 IP from opencore.org. In the core "`include" can be compiled normally, but when i include my own file the core could not compiled normally. when I remove the "`include" and move all design files to a list, they can be compiled normally. The tool what I use is modelsim. I meet these situation many times. I don't know the reason.
do anyone tell me.
thank you very much!
 

Re: question about how to use "`include" in verilo

It's the same as used in C language.

Please pay attention to the "path" used by the include.

Without giving the correct directory path of the file, include cannot find the file.
 

Re: question about how to use "`include" in verilo


Use vlog +incidr+<Dir_Where_Your_Include_file_exists> file.v

HTH
Ajeetha, CVC
www.noveldv.com
 

Also, you can use ncverilog +incdir+path
"path" is where the files you want to include is. If you have more than one paths, you can just type them together, with "+" between them.
 

If I do not write "include" in RTL code. How the tools handle it? Such as modelsim/questa/synplify ?
 

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