question about how to reduce ground bounce (switching noise)

[phosphor_zhu]

bond wire inductance qfn ground

Recently, i simulate my circuit with package model, in which the digital ground and analog ground share the same pin GND. now, the problem came out, they
have impact on each other, in the end the circuit can not work correctly. how can i do ? can anyone help me ?

thanks alot!

 

[milkdragon]

Re: question about how to reduce ground bounce (switching no

The best way is to have seperated bondwire and bondpad for analog and digital ground.

 

[northeast1]

Re: question about how to reduce ground bounce (switching no

add large decoupling cap.

 

[phosphor_zhu]

Re: question about how to reduce ground bounce (switching no

The best way is to have seperated bondwire and bondpad for analog and digital ground.

er, i have thought about that ,but i didnot know how many bonds can i parallel.

simply to me, i want to know how small the parasitic ESR and ESL can be ?
can you tell me ?

Added after 35 minutes:

Thank you !
i now give the bond wire PAD parasitic parameter as follow .

ESR 0.1ohm
ESL 1NH
pararistic capacitor is 0.5p

and i am not sure the parasitic value given is suitable .

 

[milkdragon]

Re: question about how to reduce ground bounce (switching no

The way i look at it is to calculate the impedance path from, say digital bond pad, to the clean ground path and compare with the possible impedance path from digital ground to analog ground.

For the bondwire resistance, i always assume 0.2-0.3ohm/mm and its corresponding inductance to be ~1nH/mm. So, depends on what kind of package you are using may result in different bondwire inductance and resistance. for example, if you have QFN package which provide you a ground plane, may have a downbond with inductance ~0.7nH. For BGA, which you may have more routing on the BGA substrate may give you more inductance. Thus, double bond or even triple bond may required for good isolation in this situation.

 

[phosphor_zhu]

Re: question about how to reduce ground bounce (switching no

The way i look at it is to calculate the impedance path from, say digital bond pad, to the clean ground path and compare with the possible impedance path from digital ground to analog ground.

For the bondwire resistance, i always assume 0.2-0.3ohm/mm and its corresponding inductance to be ~1nH/mm. So, depends on what kind of package you are using may result in different bondwire inductance and resistance. for example, if you have QFN package which provide you a ground plane, may have a downbond with inductance ~0.7nH. For BGA, which you may have more routing on the BGA substrate may give you more inductance. Thus, double bond or even triple bond may required for good isolation in this situation.

Thanks . but i can not understand clearly. Can you show me a example about that ?

Can any reference book i need to read?

 

[milkdragon]

Re: question about how to reduce ground bounce (switching no

You may refer to the last chapter of Design of Analog CMOS integrated circuits by Behzad Razavi

 

[phosphor_zhu]

Re: question about how to reduce ground bounce (switching no

You may refer to the last chapter of Design of Analog CMOS integrated circuits by Behzad Razavi

thank you.