QuestaSim do not support show objects value in SystemVerilog

[franklin373]

I use QuestaSim 6.4c, I debug SystemVerilog code, after reach BreakPoint, I choose instance in WorkSpace, But I cannot see value on Objects Window.

To explain, I use a very simple example:



cls_compile_test.sv:
----------------------------------------------------------------------------
`timescale 1ns/1ns
program automatic pd;

class Abc;
logic m_abc;
extern function void do_jack();
endclass:Abc


function void Abc::do_jack();
Abc cell1;
endfunction


initial begin
Abc abc;

abc=new ();
abc.m_abc=1;
abc.m_abc=0;
end

endprogram : pd
-----------------------------------------------------------------------------


compile_questa_sv.f
------------------------------------------------------------------------------


+incdir+../sv
+incdir+../../../src
cls_compile_test.sv
------------------------------------------------------------------------------





run_questa.do
-------------------------------------------------------------------------------------
##############################################################################
# Source: fcov.do
# Date: August 23, 2006
# Modified: September 20, 2006
# File: Tcl simulation script for running Questa/ModelSim
# Remarks: Questa 6.2 interleaver demo: SV Functional Coverage
##############################################################################
onbreak {resume}
if [file exists work] {
vdel -all
}
vlib work
vlog -Epretty pp_result2.txt -suppress 2167 -suppress 2181 -sv -f compile_questa_sv.f
vopt +acc pd -o dbgver
vsim +nowarnTFMPC dbgver
#vsim -sv_lib {\F:/vmm-1.1.1a/shared/bin/win32/vmm_str_dpi} +nowarnTFMPC dbgver
#vsim -sv_lib vmm_str_dpi +nowarnTFMPC dbgver
# add wave -group "Interleave DUT" /top/dut/*
configure wave -signalnamewidth 1
run -all
fcover report -cvg -comments -option -file fcover_report.txt -r *
---------------------------------------------------------------------------------------------




QuestaSim> do run_questa.do
....


Do not finish simulate after let you choose to Finish Vsim, and select instance:

VSIM 69> env
# sim:/pd/Abc

VSIM 70> show
# SVClass Abc {
# {Register m_abc}
# {Program ..}
# {Function new}
# {Function do_jack}
# {Function post_randomize}
# {Function pre_randomize}
# {Task constraint_mode}
# }

VSIM 72> exa m_abc
# null


And Objects Window do not display instance Abc's objects.


I read the document "questa_afv_tut.pdf", but it only has Verilog and SystemC simulate example, no SystemVerilog example, I read the document "questa_afv_ref.pdf", in examine command, it only said objects of VHDL Verilog C SystemC could be examined, no SystemVerilog.

Whether QuestaSim do not support show objects value in SystemVerilog debug?