Query: Power MOS in a LDO

[Apollo13]

ldo linear region

Hi All,
I have a small query, please help in sorting it out.
Is it a must to have the power mos of a linear regulator in saturation region.

e.g Vin=1.5V Vout=1.2V Iload=800mA

 

[jutek]

ldo +mos

Hi All,
I have a small query, please help in sorting it out.
Is it a must to have the power mos of a linear regulator in saturation region.

e.g Vin=1.5V Vout=1.2V Iload=800mA

no it's not a must, but if you want to have good line rejection you have to ensure work in saturation region

 

[smartdream]

NO must, but the Rdson must be meet your max loading current .i.e 800mA, to ensure not entering the dropout region. and ensure the excellent line regulation.

 

[jet_xiang]

if the power device length <1um , the saturation area not the Vds>Vgs-Vth. you can simulation to get the really area.

 

[johnsmith101]

The power MOS should not be in saturation; it should be in the linear region. You want as little drop as possible across the drain and source.

 

[eldo]

I agree with jutek. If you need good PSRR... etc, stay in saturation region. For dropout consideration, you should keep VGS-VT low.

 

[Chethan]

The pass transistor has to be in saturation , i think. coz if it is not in saturation region and is in linear region then the pass transistor fails to maintain a constant voltage at the output.

 

[engrvip]

it should not be in saturation region atleast at that will mean lot of VDS drop which u dont want in LDO.moreover try to operate it in weak inversion that will reduce ur VDS drop and provide useful gain.

Added after 14 seconds:

it should not be in saturation region atleast ,as that will mean lot of VDS drop which u dont want in LDO.moreover try to operate it in weak inversion that will reduce ur VDS drop and provide useful gain.