[SOLVED] Query: Error in clock divider used in VGA Controller (Verilog) Basys 2 board

[sukanya28]

Query : Error in clock divider used in VGA Controller ( Verilog ) Basys 2 board

Hi, I am getting an error while incorporating clock divider ( 40 MHz ) in VGA Controller ( Basys 2 board ). I have also attached the snapshot of the error shown in my coding. Please help.

The code is as follows :


module anymodule(input wire clk,reset,
output wire hsynch,vsynch,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output video_on);


// defining constants
localparam HD = 800; // horizontal display area
localparam HF = 40; // front porch (right border)
localparam HB = 88; //right porch (left border)
localparam HR = 128; // horizontal retrace
localparam VD = 600; // vertical display area
localparam VF = 1; // front porch (bottom border)
localparam VB = 23; // back porch (top border)
localparam VR = 4; // vertical retrace

wire pixel_tick;


//clock divider

// Instantiate the module
clkdiv instance_name (
.CLKIN_IN(CLKIN_IN),
.RST_IN(RST_IN),
.CLKFX_OUT(pixel_tick),
.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
.CLK0_OUT(CLK0_OUT),
.LOCKED_OUT(LOCKED_OUT)
);




//horizontal and vertical counter

reg [9:0] h_count = 0;
reg [9:0] v_count = 0;
wire [9:0] h_end,v_end;

assign h_end = HD+HF+HR+HB-1;
assign v_end = VD+VF+VR+VB-1;


always @(pixel_tick)
if(h_count<h_end)
h_count <= h_count+1;
else
h_count <= 0;


always @(*)
if(pixel_tick & h_end)
if(v_count<v_end)
v_count <= v_count+1;
else
v_count <= 0;
else
v_count <= v_count;


assign hsynch = ((h_count>= HD+HF-1) && (h_count<=HD+HF+HR+HB-1));
assign vsynch = ((v_count>=VD+VF-1) && (v_count<= VD+VF+VR+VB-1));
assign video_on = ((h_count <HD) && (v_count<VD));

wire [9:0] pixel_x,pixel_y;
assign pixel_x = (video_on)? h_count : 'b0;
assign pixel_y = (video_on)? v_count : 'b0;


reg [7:0] coloroutput;


always @(pixel_tick)
if(~video_on)
coloroutput <= 0;
else
begin
if(pixel_y<160)
coloroutput[7:5] <= 3'b111;
else if(pixel_y<320)
coloroutput[4:2] <= 3'b111;
else
coloroutput[1:0] <= 2'b11;
end


assign red = (video_on)?coloroutput[7:5] : 3'b000;
assign green = (video_on)?coloroutput[4:2] : 3'b000;
assign blue = (video_on)?coloroutput[1:0] : 3'b000;


endmodule

 

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Re: Query : Error in clock divider used in VGA Controller ( Verilog ) Basys 2 board

You're only using one connection on the clkdiv sub-module. You aren't driving the inputs clock CLKIN_IN or RST_IN.

Regards

 

[mrflibble]

Re: Query : Error in clock divider used in VGA Controller ( Verilog ) Basys 2 board

This bit:

---

Code Verilog - [expand]
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// Instantiate the module
clkdiv instance_name (
    .CLKIN_IN(CLKIN_IN), 
    .RST_IN(RST_IN), 
    .CLKFX_OUT(pixel_tick), 
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
    .CLK0_OUT(CLK0_OUT), 
    .LOCKED_OUT(LOCKED_OUT)
    );

---

You don't declare any of those signals anywhere. And the really fun part about verilog is that it will happily make up new shit as it (and you) goes along. Make a typo in a signal name? Nooooo problemo! You now have the typo-ed version as well, congratulations. And it will by default be a 1-bit wire. So in your above code you just conjured up the CLKIN_IN signal out of thin air. Well, all the other signals as well, but it's the CLKIN_IN signal that is responsible for that error message.

As you noticed this behaviour makes certain coding styles rather prone to errors. In this case the cop/paste coding style. You copied the module instantiation template (which is good), and then you just hoped for the best (which turned out to be bad).

After you copy/paste the template, you should change the signals to something in use by your design.

To avoid this type of thing (and other annoyances) I always put `default_nettype none as first line of a verilog file and `default_nettype wire as the last line. That way you will get actual error messages when you forget to declare signals, instead of sneaky silent failures.

So in this case you will have to change the signal names used by your aptly named "instance_name" instance.