Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
clock latency gives the delay in the clock signal to travel from the clock generation port to the clock pin of FF.... propagated delay is the delay when it the clock latency is varying i.e. the clock latency cant be the same for the clock pin of all the FFs....
Before CTS we just have ideal clock network..i.e. no skews, no clock latency(network or propagated), thus we provide an uncertanity value to model(clock skew + jitter)..POST CTS we have a realistic clock network wid realistic delays, and skew information. Thus the uncertanity value post CTS models only jitter. Plz correct me if iam wrong...
1. ideal clock latency has 2 parts:
a. ideal Clock source latency which is implemented by command set_clock_latency -source 2 clk
b. ideal clock network latency which is implement by command set_clock_latency 1 clk
2. propogatted clock:
a. clock soure latency still is valid. (set_clock_latency -source)
b. network latency is path delay from clock source port to sink pin of FF. which is implemented by command set_propgated_clock
3. clock uncertainty is different term.
it is the amount of time variation in successive edges of a clock or between edges of different clocks. It captures the actual or predicted clock uncertainty.
it is modelled by set_clock_uncertainty
4. derate/AOCV is not only for clock, it also can used for data path. it is similar with uncertainty to modle the variation of arrival time or delay
it is implemented by set_timing_derate or read_aocvm etc,