query abt clock latency

[vishalkatba]

what is the difference ideal clock latency and propagated clock latency ?

 

[megastar007]

The propagated clock latency is nothing but network latency i.e latency from clock port to your clock pin of FF.

source latency is the latency form clock source to your clock port.

Before CTS, clock uncertainity constraint includes this network latency + jitter

After CTS, no need to add network latency(clock uncertainity is only jitter now) it is included if you use propagated clcok.

Added after 4 minutes:

The propagated clock latency is nothing but network latency i.e latency from clock port to your clock pin of FF.

source latency is the latency form clock source to your clock port.

Before CTS, clock uncertainity constraint includes this network latency + jitter

After CTS, no need to add network latency(clock uncertainity is only jitter now) it is included if you use propagated clcok.

 

[ubna]

Ideal clock latency are those delay included in your RTL design.
Propagated clock latency comes due to physical parameters like pin resistance,skew,wiring to the chip....

 

[A.Anand Srinivasan]

clock latency gives the delay in the clock signal to travel from the clock generation port to the clock pin of FF.... propagated delay is the delay when it the clock latency is varying i.e. the clock latency cant be the same for the clock pin of all the FFs....

 

[anas66]

I have a doubt ?? Crrect me if i am wrong ... The uncertanity values includes the (clock skew + jitter) right and not (network latency + jitter), right ?????

 

[jeevan.life]

I think v include n/w latency also with the margin...and also the OCV effects...any corrections?

 

[geek09]

I have a doubt ?? Crrect me if i am wrong ... The uncertanity values includes the (clock skew + jitter) right and not (network latency + jitter), right ?????

I think you are correct..

Before CTS we just have ideal clock network..i.e. no skews, no clock latency(network or propagated), thus we provide an uncertanity value to model(clock skew + jitter)..POST CTS we have a realistic clock network wid realistic delays, and skew information. Thus the uncertanity value post CTS models only jitter. Plz correct me if iam wrong...

 

[jeevan.life]

Is it only clock skew +jitter??? dont we also include latency and OCV things??

 

[geek09]

Is it only clock skew +jitter??? dont we also include latency and OCV things??

OCV is modelled by derating factor, uncertanity is independent of OCV. Correct me if iam wrong.
Latency is modelled by set_clock_latency, not by uncertanity.

 

[phoenyxu]

1. ideal clock latency has 2 parts:
a. ideal Clock source latency which is implemented by command set_clock_latency -source 2 clk
b. ideal clock network latency which is implement by command set_clock_latency 1 clk

2. propogatted clock:
a. clock soure latency still is valid. (set_clock_latency -source)
b. network latency is path delay from clock source port to sink pin of FF. which is implemented by command set_propgated_clock

3. clock uncertainty is different term.
it is the amount of time variation in successive edges of a clock or between edges of different clocks. It captures the actual or predicted clock uncertainty.
it is modelled by set_clock_uncertainty

4. derate/AOCV is not only for clock, it also can used for data path. it is similar with uncertainty to modle the variation of arrival time or delay
it is implemented by set_timing_derate or read_aocvm etc,


Regards
Liwen