heey all,
i've done writing a vhdl code on Quartus || but i faced this problem
when i simulate in functional simulation mode, the circuit is doing well and the output comes as it's expected!
but when simulating the whole code on Timing mode, the circuit seems not to function correctly and the output is wrong for the same input of the above iteration!
if the problem is due to delay, please tell me how can i solve it
and will i face problems when downloading the code on FPGA ?
...
Thanks in advance!
---------- Post added at 20:50 ---------- Previous post was at 20:25 ----------
Please all, i would be very grateful if you could help me in my project
1) Your timing simulation is not being setup and/or run properly, or
2) You have timing issues. When you compile your design do you get any timing errors? Have you set your timing constraints properly?
I don't use Altera any more (because their support is the worst) so I'm not really familiar with their recent tools, but I think you need to use Timequest to set the timing constraints. What is your clock frequency?