Quartus || - Timing simulation problem

[MAAASD]

heey all,
i've done writing a vhdl code on Quartus || but i faced this problem
when i simulate in functional simulation mode, the circuit is doing well and the output comes as it's expected!
but when simulating the whole code on Timing mode, the circuit seems not to function correctly and the output is wrong for the same input of the above iteration!
if the problem is due to delay, please tell me how can i solve it
and will i face problems when downloading the code on FPGA ?
...
Thanks in advance!

---------- Post added at 20:50 ---------- Previous post was at 20:25 ----------

Please all, i would be very grateful if you could help me in my project

 

[barry]

It sounds like either of two issues:

1) Your timing simulation is not being setup and/or run properly, or
2) You have timing issues. When you compile your design do you get any timing errors? Have you set your timing constraints properly?

 

[MAAASD]

i don't know how to set the timing constraints

 

[guguwuwu]

Maybe you should join a global clock to the code. If it is necessary, you can change your code into synchronous logic.

---------- Post added at 08:43 ---------- Previous post was at 08:41 ----------

It's difficlut to identify specific problem without any codes.

 

[barry]

i don't know how to set the timing constraints

Well, there's your problem. You need to read up on constraints and how to set them. At the very least you need to set a maximum frequency requirement.

 

[MAAASD]

If you could tell me how can i set a maximum frequency requirement i would be very grateful i've just searched for it
i didn't get what i want!

 

[barry]

Look at this. http://quartushelp.altera.com/9.1/mergedProjects/analyze/sta/sta_pro_constraints.htm

I don't use Altera any more (because their support is the worst) so I'm not really familiar with their recent tools, but I think you need to use Timequest to set the timing constraints. What is your clock frequency?