My first question is - why? Do you have a target clock speed you're trying to acheive? or is this just an academic exercise to see what fmax you can actually acheive?
What clock speed requirement have you set? Often, if you over-constrain the clock, it makes the fitter work harder. But if its too far overconstrained, the fitter can give up early. So, do you have a target clock you're not achieving?
If you do acheive a higher fmax - how does this benefit you? can you actually increase the clock speed? why not just try with this higher clock speed in the first place. Again, if you underconstrain a design, it will stop when it achieves the desired goal.
So here, it is usually just best to set your desired FMax in the first place, and then put effort in if you fail to meet this timing. Surely you have bandwidth or clock requirements somewhere on the IO? so having a higher clock speed internally probably wont be much benefit, as the IO cannot take the extra data.
Using the logic locks should really only be a last resort to meet your timing requirements. If you lock everything down in the first instance, when you add some new logic functions, you're making it harder to route as you're potentially limiting the fitter's options for the new logic.
To your actual problem - the only way would be tcl scripts, and sensible path naming. With decent naming, you can simply lock everything in some loops. But this might be hard because it will be unlikely to get nice names/locations for the regions.
The chip planner does allow you to draw and move the regions in the gui (although I havent done this for a few years).