zoulzubazz
Member level 5

hey guys,
new to vhdl design and i think the error is due to something trivial, following is the vhdl code for which i want to generate a rtl diagram using rtl viewer in quartus 2. I get the following error when compiling the code
new to vhdl design and i think the error is due to something trivial, following is the vhdl code for which i want to generate a rtl diagram using rtl viewer in quartus 2. I get the following error when compiling the code
As you can see the code is simple and should compile ok but it isnt. thanks.12006 Error: Node instance "rcvr" instantiates undefined entity "spi_custom_slave"
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spi_custom is port ( ss : in std_logic; clk : in std_logic; MOSI : in std_logic; outs : out std_logic ); end entity spi_custom; architecture behave of spi_custom is component spi_custom_slave port( ss : in std_logic; clk : in std_logic; MOSI : in std_logic; outs : out std_logic ); end component spi_custom_slave; begin rcvr: spi_custom_slave port map ( ss => ss, clk => clk, MOSI => MOSI, outs => outs ); end architecture behave;
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