Ranand
Newbie level 5
Hi,
Is there any thumb rule to set the Quantization threshold for generating the bitstream while modeling a first order sigma delta ADC?
I am trying to model a 16 bit SDM ADC with a full scale input of of 1Vrms.
Thanks,
Ranand
Is there any thumb rule to set the Quantization threshold for generating the bitstream while modeling a first order sigma delta ADC?
I am trying to model a 16 bit SDM ADC with a full scale input of of 1Vrms.
Thanks,
Ranand