Ranand
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Hi,
Is there any thumb rule to set the Quantization threshold for generating the bitstream while modeling a first order sigma delta ADC?
I am trying to model a 16 bit SDM ADC with a full scale input of of 1Vrms.
Thanks,
Ranand
Is there any thumb rule to set the Quantization threshold for generating the bitstream while modeling a first order sigma delta ADC?
I am trying to model a 16 bit SDM ADC with a full scale input of of 1Vrms.
Thanks,
Ranand