Quad port design from two Dual port BRAMs

[SharpWeapon]

Hello,

Is there anyone who have tried to construct a Quad port RAM from two Dual port BRAMs? I couldn't find enough resource on it, so grateful if anyone can drop me fragment of the vhdl code.

PS: you can have a look of my code for it in my previous post(https://www.edaboard.com/threads/320193/) . For that code the synthesizer understood that I am looking for a Quad port but it is implementing it using Distributed RAM, I tried to force the synthesizer by changing the HDL synthesis option to Block RAM, I have the following warning message:

Cannot use block RAM resources for signal <Mram_ramMem>. Please check that the RAM contents is read synchronously.

Thanks!

 

[ads-ee]

Drat, You beat me to it. I was going to propose a community challenge to design a quad port memory using block RAM.

I think this is only doable if the clock used to perform writes is 2x the write side interface clocks. Writes are the peeformed as follows:
Phase1 i/f 1 writes to ram1, i/f 2 writes to ram2
Phase2 i/f 1 writes to ram2, i/f 2 writes to ram1.

This will keep the contents of the ram coherent.

Regards

 

[SharpWeapon]

I decided to take another approach for it, than going through all the complexity you suffered. Fortunately, the new one succeed, hope you had fun with the Quad port