Q Factor Of OTA C Biquad

[samiran_dam]

Dear All,

I am designing a OTA-C Biquadratic Filter (Butterworth Approximation) stage. The topology is:

For this topology, filter cut-off frequency and Q-factor is defined by:

2*π*ω=gm/√(c1*c2) [gm1=gm2=gm]
Q=√(c2/c1)

For 200 KHz filter cutoff frequency and Q=1.93, I calculated c1 and c2 values as 15.67 pF and 58.36 pF respectively given gm=38.17 uA/V. When I simulated the circuit with a simplistic OTA model (with non-zero output conductance and non-zero output parasitic capacitance included in the model), it produced desired values of cut-off frequency and Q factor.

But when I realized a transistor-level circuit, although filter cut-off frequency is 199.98 KHz, Q is 1.85. From the DC analysis I have confirmed that the gm value is exactly 38 uA/V for the transistor-level OTA used. And the output conductance considered in the model-based simulation are same as the output-conductance delivered by the transistor-level circuits. Q is simply defined the ratio of two external capacitors. I am unable to identify which non-ideal factor of the OTA is affecting the Q to be degraded. If somebody has any idea about this, please help me.

regards
Sam

 

[LvW]

Dear All,
...........................
Q is simply defined the ratio of two external capacitors. I am unable to identify which non-ideal factor of the OTA is affecting the Q to be degraded. If somebody has any idea about this, please help me.

It is not correct to say that "Q is simply defined the ratio of two external capacitors".
The definition of Q is based on circuit theory - and when this theoretical definition is applied to a particular circuit a formula results that allows to design the wanted Q value. However, this formula - as in your case - is based on ideal amplifier properties.
Otherwise, the formula would be much more complicated than in your case.
Thus, it is no surprise that Q deviates from the ideal value when real circuit elements are used.
More than that, since your simple formula assumes some certain relationships/ratios between the resistors (that cannot be met exactly because of tolerances) even resistor uncertainties cause additional Q deviations.
If you cannot live with these "errors" you have to adjust some components correspondingly.

 

[samiran_dam]

Yes I am aware of the fact that circuit non-idealities affect the performances. Intention of my initial post was to get some idea of what OTA non-ideality could affect the Q factor apart from non-zero output conductance and non-zero output parasitic capacitance. As I have already mentioned those two most important non-idealities are included in the model with which I simulated the circuit and got almost the values defined by the ideal set of equations. So in transistor-level realization, what else is coming into the picture which is affecting the Q.

 

[LvW]

OK, so we are on the same line now.
Well, if output OTA impedances are considered already, I think there only remain non-ideal OTA-input impedances as well as transconductance matching errors (only now I realize that there are no lumped resistors in your cicuit).
But the question arises: How did you include non-ideal output conductance in the Q calculation? Because 1.93 rersults from the capacitor ratio only.
What about capacitor quality?
Beside this, I do not consider the difference between 1.85 and 1.93 as surprising.

 

[samiran_dam]

1. I have checked that transconductance are well matched.
2. I have not calculated the effect of non-zero o/p conductance in Q measurement. I just simulated in SPECTRE.
3. Capacitors are perfect.

I also expect this deviation, but wondering which factor is responsible for the deviation. If this deviation also appears in model-base simulation then I would have appreciated it. But the mismatch between the model and transistor-level is annoying me. I have checked the validity of the model. May be I need to work out some calculation on pen & paper.

 

[LvW]

I would prefer some "trial and error" investigations based on simulation. Pen & paper is to complicated and time consuming, for my opinion.
What about some ideal OTA's that are equipped "step by step" with some parasitics?
By the way, lumped transistor circuits at 200 kHz do suffer, of course, from parasitic capacitances that are part of the physical construction.

 

[samiran_dam]

Hi,

I am experiencing a problem for which I am not able to identify the reason. Please have a look at this:

It means that the poles will surely be in the LHP of s-plane provided it is complex-conjugate.

But in the simulation I am finding the complex-conjugate poles to be at RHP, though the magnitude of pole frequency and pole Q are coming same as calculated from the equations. The values I have considered: gm1=gm2=38.17 uA/V, C1=15.67 pF, C2 = 58.36 pF.

The OTA block I have considered in the simulation consists of a simple VCCS, nothing else. I have verified the polarity and other working conditions of the OTA block to be correct.

Could someone please explain the reason behind this weird behavior? Please point me out to the incorrectness in the analysis, if any.

regards
Sam

 

[LvW]

Hi Sam,
two questions:
1.) Which simulation did reveal the RHP poles?
2.) Did the circuit saturate or oscillate in tran analysis?
Perhaps I have time today to do some simulations by myself.
LvW

---------- Post added at 11:53 ---------- Previous post was at 11:14 ----------

Hi Sam,

at first, the circuit and its dimensioning is, of course, correct.
My simulation results (VCCS ideal) are OK and as expected.
Perhaps your OTA(s) output current has not the correct direction?
In my simulator the positive and negative input/output nodes are not in the same configuration (up/down) - and this has to be considered correctly.

 

[samiran_dam]

Hi LvW,

Yes, man you are right.

It was fault from my part. the direction was not right. Actually vccs was written in VerilogA and in that snippet I put a minus sign driven by a wrong concept I had. I just discovered that after lots of unnecessary debugging efforts to find such silly mistake. Anyways thanks for the confirmation. :lol:

regards
Sam

 

[LvW]

Hi LvW,
Yes, man you are right.
It was fault from my part. the direction was not right. Actually vccs was written in VerilogA and in that snippet I put a minus sign driven by a wrong concept I had. I just discovered that after lots of unnecessary debugging efforts to find such silly mistake. Anyways thanks for the confirmation.

Yes, such things (silly mistakes) happen from time to time.
Once I forgot to remove the initial voltage from a capacitor before starting an ac simulation. As a result - the bias point was not correct and it tooks me about half a day to locate this error.
Nevertheless, good luck.
LvW

 

[samiran_dam]

Hi LvW,

Back to the initial question -

I have observed that due a 3 mV offset there is a mismatch between the gm values of the input transistors pair which are supposed to be matched. Though the mismatch is not that significant - 38.17 uA/V and 38.25 uA/V. Do you think that this small mismatch is resulting the deviation?

Please help.