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PWM filtering (~240Hz)

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TalhoSan

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Hi!
Sorry for bothering everyone, but I would like to ask some help/guide!

I have a high resolution (16bit) PWM signal (3.3V Vpp, ~5mA), but the signal frequency is only around ~240Hz. The problem is that I have to filter this low frequency signal, to make it more like an analog signal. Even an active Low Pass Filter by itself doesn't help much. In some later stages I can filter out the higher harmonics of the filtered PWM, but the low freq can still be measured even on other stages.

Decreasing the resolution at some extend can work and I can solve the filtering in that case, but I would like to know if someone knows a way, to help the original signal.

From time to time I have to change the output, but not every millisecond, but I have to change it almost accuracy of milliseconds.

Actually I have at least 8 independently controlled PWM (at least 14 bit, but they prefer 16 bit) signals. I know, that making this ~240Hz PWM into a perfect analog signal is not possible, but I would like to get rid of most of the ~240Hz noise.

In another forum I've already got some ideas, but they are not usable for a reason. Here's a list from those ideas:
#1 Using DACs
#2 Integrated Filter ICs
#3 Different MCU, FPGA/CPLD

So I would like ideas about how to filter the PWM signals. I already solved the problem in a lower resolution, which is still acceptable, but I would like to know if somebody have another idea.

Thank you for help.
 

Use a higher order low-pass active filter. The free program FilterPro from Texas Instrument allows you to easily design high-order active filters.

What is the order and the corner frequency of the filter you tried?

What is the minimum time you need for an output change to settle to its new value? You mentioned milliseconds but how many milliseconds? Vague requirements make for vague designs. ;-)
 

Thank you for your help!
I already tried FilterPro, but the result it gave me is mostly has 5 or more stages. I mostly tried 2nd and 3rd order filters. My old University ordered this equipment and they have some almost unreasonable demand (mainly about money). So filters that is more than 2 stages is not a good way, since I have to make 8 of them and that could increase the component expenses, not to mention that it will make the PCB designing much more complex. I don't think that they will pay for it.

I know that I didn't gave every single detail about the requirements, but I don't want you or someone else to do my job instead of me. I want to do it, but I would like to hear some ideas. But if you want to know, then I tell you. The settling time has to be below 5 milliseconds.

Thank you for your help!
 

Your combination of PWM frequency, response time, and resolution makes for a very difficult design. For a ripple of 1 LSB for 16-bits means you have to suppress the ripple by 96dB. That requires a high order of filter for that amount of rolloff between the 5 ms response time, which implies a frequency response of better than 32Hz, and the 240Hz PWM frequency.

I don't see you easily getting there without a very high order of filtering unless some of the parameters are relaxed.

Why can't you use an integrated filter IC?
 

Lowering the resolution is possible and acceptable. By lowering it the PWM frequency will be higher and I already made a prototype for that, and it works. But I'm not going to use a high order filter if they are not going to pay for it.

The reason for not using integrated filter IC is the money. The University gave me a budget. I need to use at least 8 completely independent PWM signal and I have to filter out every one of them independently. The University will pay only for components, that was ordered from my country and even with the cheapest filter ICs I will be way above the budget. So it's out of the question. You could say that the budget is quite unreasonable. The reason for DACs and FPGA/CPLD is similar.

The requirements are set high, since they will use this product for a research, but they used up most of the money.

Anyway thanks for you help!
 

Well I can buy those ICs, but they will not pay for it since it will be above the budget, so I have to pay them from my own pocket, which comes from my profit. I can still do the job, since 14 bit is the least minimum that they need, but I'm looking for ways to do it with higher resolution, but still staying within the budget.

With 14bit the frequency is higher, which is easier to handle. I already made a prototype with 14bit, measured the output with a scope, and it's fine. So the I could say, that the job is done. I just trying to find a way to make it better. So I'm not really loosing anything here.

Anyway, thanks for the help!
 

TalhoSan said:
.............................

With 14bit the frequency is higher, which is easier to handle. I already made a prototype with 14bit, measured the output with a scope, and it's fine. So the I could say, that the job is done. I just trying to find a way to make it better. So I'm not really loosing anything here.
Click to expand...
What does the PWM frequency have to do with the resolution? :-?
 

Unfortunately not every MCU has a fixed PWM frequency. Most of them has an inverted proportion between PWM resolution and frequency. Unfortunately I don't have programmer for MCU that has fixed frequency and I'm not going to buy one for just one job. So my hands are tied, I can only use MCU, that I can program.
By decreasing the resolution I can increase the frequency and it works that way, since the datasheets says it, and I measured it too, so it's true. But that's part of the digital system, not the analog. I'm already clocking the MCU and Timer modules (PWM) with the maximum allowed frequency.

Here you can find a table, which can show, that PWM resolution and freq is inversely proportional. It's not the one I'm using, but this was faster to put in here:

https://www.digikey.com/Web%20Export/techzone/power/power-article-110707-2.jpg
 

I have to change it almost accuracy of milliseconds
Click to expand...

What does this statement mean? PWM period is already 4.2 ms, response time after a filter will be surely larger than PWM period. A filter with sharp pass-to stopband transition has unfortunately a ringing response in time domain, I guess you won't want it.

I see this options:
- accept the settling time of a filter with reasonable specification
- use a sample-and-hold stage after the filter. Unfortunately you get a certain non-linearity
- use a DAC method with less low frequent ripple, e.g. sigma delta.
 

FvM!

about the quote:
The equipment has to old it's PWM Duty-Cycle for a presetted (can be changed by the user with a PC) amount of time. But it could be easier to understand with an example.
The user set the system to hold PWM Channel 1 for (let's say) 2Hours 4Minutes 34Seconds and 18Milliseconds. The systems accuracy about when to change the Duty-Cycle has to be in a milliseconds level. Sometimes they will turn off the PWM CH1 after the presetted time has passed, sometimes they will change the Duty-Cycle. There will be times, when the system has to go for days, sometimes just for a few hours.

About the options you gave me:
#1 Most of the specification was give as minimum requirements. So there are a lot of things that I cannot change even if I want to.
#2 Certain amount of non-linearity is acceptable. I didn't looked into this method, so I will look into this.
#3 DACs could be great, but the budget is too low and they aren't going to fit in. I'm optimizing the system, since I'm currently way ahead of schedule, I have time for this. If I can make some parts cheaper then I already thought about using DACs or Integrated Filter ICs.

Thanks for your help!
 

With "DAC", I was referring to all methods generating an analog signal from digital data, also the now utilized PWM DAC. Sigma-delta DAC meaned a method, where a digital pin sends a binary pulse sequence with an average representing the analog value.

It's however true that a DAC IC should be considered as simple and straightforward solution. It will occupy less board space and consume less power than the analog filter required for the PWM method.
 

Well as long the budget doesn't allow it not much can be done with DACs, but I'm still reviewing the system about where can I cut something.

In another forum I just got an idea(not my idea) of using R2R-DAC with serial->parallel ICs. I'm not of using 8 serial communication protocol with parallel with critical timing, but I have the most expensive components for it in stock. All I need is the resistors (1% or below) and run some tests. Then well see what will happen.

Thanks!
 

R2R is an option, but can't give 16-Bit accuracy. A PWM DAC with lower resolution and moderate filtering might be better.
 

PWM DAC could be better, but making my own R2R DAC isn't going to cost me much even with 0.1% resistors (I looked up some shops in the meantime). I already have the most expensive parts, all I need is th resistors. Making some test wouldn't hurt me much.
 

TalhoSan said:
PWM DAC could be better, but making my own R2R DAC isn't going to cost me much even with 0.1% resistors (I looked up some shops in the meantime). I already have the most expensive parts, all I need is th resistors. Making some test wouldn't hurt me much.
Click to expand...
0.1% resistors will give a worst-case accuracy of about 10-bits which is well below your requirements.
 

As I said it show that the frequency is inversely proportional to resolution. And I also said that it's not the one I'm using, this was faster to put in here. Currently I'm not in the mood of "Photoshopping"/cutting and uploading screenshots. So it served its purpose just right, it shows what it has to. In my case the 16bit resolution has around 240Hz frequency, while the 14 bit has a little above 1kHz. It was to show Crutschow that the resolution and the PWM frequency is not independent from each other.

Even if we are speaking in kHz, the proportion is inverted between the resolution and the frequency.

Lilianj!
What do you want to know more about?
 
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