Hi,
I'm not saying the half-bridge mode would cause the error, but rather the starting phase of the pwm output when the duty cycle is written, which would exist even for a single PWM output (At least that is what I think would happen, since the pwm clock is at a different frequency to Fosc, and writing a new duty cycle to the pwm register does not adjust the pwm clock phase to generate an output change immediately after the instruction - or does it??). I'm using 18F66k80, at Fosc = 64MHz, so an instruction cycle rate of 16MHz, or Tosc*4 = 62.5ns, which is an acceptable error for all timings in the output signal (Period, pulse width, start-up time, and delay between outputs going high to avoid shoot-through current in the bridge) - this is why I'm now thinking of bit banging (edited my post above^^).