Puzzle SAR ADC simulation ???

[wls]

Hello all . I am doing a 10 bit SAR ADC . Main blocks are (1) Zero off-set comparator (2) Resistor based DAC (3) SAR logic ( synthesis and P&R ) .

At cadence schematic the simulation with typical model , temp 27 it runs okay . Even running using calibre netlist with no parasitic , simulation is similar to that of circuit/gate .

The problem is post simulation with parasitic ? The simulation run correct at higher temperature ( our own model process run 0 to 125 temp , " best 0 , typical 25 and worst 125 " . The post simulation run okay with temperature 125 but not correct if lower temp used ? Why is this happenning ? When this happen does it mean it will fail during tape out ? Is it setting or model related problem ?

Regards.

 

[fredflinstone]

which part of the circuit is failing? is it a functionality error or performance degradation?

 

[wls]

Hello fredflinstone . It work but only if temperature is the worst temp stting used , 125 ? As for the blocks its all lump as single netlist , extracted from layout . Do we need to extract each block then combine as SAR ADC to check the problem ? I did it on the comparator block last time , at circuit/gate it work but when using the extracted from layout and running postsimulation with parasitic . Same result all corner run when worst temperature is used , 125 ?

Reagrds.

 

[yschuang]

Hello, wls

You used a method named auto-zero to cancel offset.
Do you take care of charge injection when designing a comparator ?

 

[fredflinstone]

hello wls,
It sure will help you if u do block level parasitic simulation. At 125 degC normally the devices gets slower... the critical path in your SAR logic is something to look at. Also the comparator may not be able to amplify the input to sufficient levels before giving to latch.