cmyeda
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Hello everyone, I'm a new guy on this forum. I am a postgraduate in Fudan University in ShangHai. I have encountered some problem about the power analysis, so I regesiter in this forum and look for some help.
My problem is here:
I designed a 2bit pipelined multiplier which is very small and the synthesis result shows it only has 20 standard cells. (smic13HT library , 1.2v supply voltage). Then I written a testbench where the clk period is 10us. And then I got the "saif" file by VCS simulation. Finally I got the power analysis result by PTPX, which shows the total power is 35nW.
To take the power analysis using spectre, I translated the verilog netlist to schematic using the cadence tool in ADE. However the smic13HT library does not provide the schematic cell view of the standard cells. It only provides the symbol cell view of all cells. So I manually draw the schematic cell views of the cells appeared in the netlist base on the CDL file (The CDL file have the spice netlist of all standard cells). Then I written a verilog testbench which is same with the previous one, and save as functional cell view. Finally, I connected the testbench with the multiplier, and started the mix-signal simulation (1.2v supply voltage). The total power of the multiplier was plotted, and average power is 377nW ! Ten times of the PTPX result !!!
Both simulation time are more than 1000 cycles, and the clock periods are same. It was expected that both results should be approximate. Obviously the experiment result was very disappoint. So what's wrong with this contrast experiment?
I hope I have not spelled wrong. Thank you very much for your help!
My problem is here:
I designed a 2bit pipelined multiplier which is very small and the synthesis result shows it only has 20 standard cells. (smic13HT library , 1.2v supply voltage). Then I written a testbench where the clk period is 10us. And then I got the "saif" file by VCS simulation. Finally I got the power analysis result by PTPX, which shows the total power is 35nW.
To take the power analysis using spectre, I translated the verilog netlist to schematic using the cadence tool in ADE. However the smic13HT library does not provide the schematic cell view of the standard cells. It only provides the symbol cell view of all cells. So I manually draw the schematic cell views of the cells appeared in the netlist base on the CDL file (The CDL file have the spice netlist of all standard cells). Then I written a verilog testbench which is same with the previous one, and save as functional cell view. Finally, I connected the testbench with the multiplier, and started the mix-signal simulation (1.2v supply voltage). The total power of the multiplier was plotted, and average power is 377nW ! Ten times of the PTPX result !!!
Both simulation time are more than 1000 cycles, and the clock periods are same. It was expected that both results should be approximate. Obviously the experiment result was very disappoint. So what's wrong with this contrast experiment?
I hope I have not spelled wrong. Thank you very much for your help!