Ata_sa16
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View attachment 148614
Try Implementing this topology. You can increase the slope of the PTAT current by increasing the number of parallel transistors, Q2.
Iptat=Vtln/R1
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I think that a beta current reference you've shown is inherently limited by its physical properties, i.e.
View attachment 148615
as explained in Baker's book
The delta-VT generator shown could work, should not be
expected to have the same slope as a diode based ptat.
Playing with the two mirror gains (ratios) is where it's at.
Also resistor species selection, for tempco contribution.
Design of Analog CMOS Integrated Circuits by Razavi, or CMOS Circuit Design, Layout, and Simulation 3rd ed. by Baker. They all talk about it almost the same way but I feel razavi is more intuitive while baker is more practical.Can you tell me the reference so I read about it.
Yes. I think npn is actually preferred (I'm not sure though), they only use lateral pnp because of the CMOS structure.Can I use diode connected npn
Have you tried increasing the number of parallel transistors of Q3? or tried increasing/decreasing the pmos mirror ratios? or tried using a resistor with negative tempco (some technologies have them).
Also, you can try using a different topology not using an opamp.
View attachment 148627
I am not a band-gap expert, however I have a doubt about biasing point of the circuit from #6.
In room temperature you have 132µA of current flowing to the silicon diode and the diode has 710mV (larger I suppose) and 807mV of drop. I think these values are too high, it means the point on the I-V curve is far from 0.65V drop (let's called it as "ideal" drop) for a silicon diode. Also you pmos current source are extremely inverted.
I would propose to decrease the biasing current by order of magnitude (at least, maybe even more).
The second thing, what kind of slope have you expecting?
Hi,
I've lost my way to the wrong section, am out of my depth, and misunderstood the premise, before someone grumpy criticises me pointlessly, TIA.
I don't know if this is of any use. And sorry it's not more than a discrete concept... I'd thought maybe skipping the mirror stage and using an (in my opinion) undesirable current source might be a simpler solution, so long as a suitable buffer can be found.
Have you considered modifying a 4 to 20mA circuit for this purpose? Voltage to current conversion, using Vbe rise and amplifying it to the range needed?
Anyway, 6 to 8.3mA from 25ºC to 65ºC:
View attachment 148739 View attachment 148740
View attachment 148741
Do you know you are doubling you power consumption with this method ?
Do you have real resistor provided by PDK ?
I cannot read your resistor values, you have 3.9 ohms ???
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