PSS fail to converge when internal clock was using

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Hi all,

I been working on a switched-capacitor DC-DC converter, and I want run pss and pac to get PSRR for my converter. When I use an ideal clock source (i.e., vpluse) to drive the converter, PSS converge fine. However, when I use my ring oscillator to drive the converter, PSS won't converge.

Here are my netlist and simulation log.

Could anyone provide me with some insights?
Thanks!
 

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Be sure you are using the true period where end = start for -all- nodes.

For example if your clock network begins with a /2 to ensure 50/50 duty, you would need to have period 2X input clock period. And that's with no subsequent divisions that would take longer to wrap back to t=0.
 

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