PSS convergence in PLL simulation

Status
Not open for further replies.
After lock time, the VCO output frequency has some spurs due to the nonlinearity of the charge pump. I think this is the reason. please correct if I am wrong.https://imgur.com/YXkq61K
 

Wrong.
Surely confirm and study your PLL.

Show me true comparison frequency and divide-ratio.
Are they truely 19MHz and 128 ?

It is too early for you to go to PSS Analysis.
 
Last edited:

Please suggest me the type of analysis, to verify the PLL.
 

kunalsan said:
After lock time, the VCO output frequency has some spurs due to the nonlinearity of the charge pump.
I think this is the reason.
Click to expand...
It can never be.
2440MHz-2432MHz=8MHz is too large.

kunalsan said:
Please suggest me the type of analysis, to verify the PLL.
Click to expand...
Transient Analysis.
 

According to https://i.imgur.com/YXkq61K.png, fout=2433.7MHz at 4.6usec.
Yout PLL is far from locked state with ~10usec.

Run Transient Analysis of Tstop=500usec.
Then show me fout at 50usec, 100usec, 150usec, 200usec, 250usec, 300usec, 350usec, 400usec, 450usec and 500usec.
 
Last edited:
Thank you for your kind consideration.
I will reply to you after doing what you have suggested to me.
yes, the comparison frequency (reference frequency) is 19 MHz and the divider ratio is 128 ( for divider I have used 7 stages of cascade TSPC latch).
 
Last edited:

Show me numeric values as list like following.

50usec : 24**MHz
...........
450usec : 24**MHz
500usec : 24**MHz
 
Last edited:

fout frequency at
50us : 2431.3MHz
100us : 2433.5 MHz
150us : 2433.5MHz
200us : 2433.2MHz
250us : 2433.3MHz
300us : 2434.9MHz
350us : 2434.4MHz
400us : 2435.1MHz
450us : 2432.9MHz
500us : 2431.1MHz
 
Last edited:

It seems Tstop=500usec is not enough to be locked state.
500usec is nearly equal to 10000cycles regarding your comparison frequency, 19MHz.
Try Tstop=1msec.

BTW, you have to save minimum node or current in PLL simulation.
Don’t save unnecessary data such as device parameters, subcurcuit infos, etc.
Show me netlist except for circuit descriptions.
 

ok, I will try with 1msec and update you with the result
netlist:-
Code: 
simulatorOptions options reltol=1e-3 vabstol=3e-5 iabstol=1e-11 temp=25.0 \
    tnom=27 multithread=on scalem=1.0 scale=1e-6 gmin=1e-12 rforce=1 \
    maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf 
tran tran stop=1m errpreset=moderate write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save fout 
saveOptions options save=selected
 

kunalsan said:
simulatorOptions options reltol=1e-3 vabstol=3e-5 iabstol=1e-11 temp=25.0 \
Click to expand...
These vabstol=3e-5 iabstol=1e-11 are different from default values.
Why do you set vabstol and iabstol as these values ?

kunalsan said:
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile

primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
Click to expand...
Delete these lines.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…