psrr issues in ldo design

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ldo design psrr

hi,all
i have some questions about psrr in ldo design
1. if there are 3 sub-modules in my ldo , then psrr of ldo depends on the minmum psrr of the sub-module ,is that right ?
2. first i checked my bandgap's psrr. i wanna a psrr of 60db@10k,however ,in my design, only 57db@10k. then i checked the psrr of the opamp used in bandgap.which is 60db@100k and meets my needs. so how can i improve my psrr of bandgap without increase the Ac gain of opamp

anyone could give me some advice ?
suggestions and advice will always be welcome, thx a lot
 

how to reduce psrr

You can check the following two theses:

A Capacitor-less Low Drop-Out Voltage Regulator

**broken link removed**


An Accurate, Trimless, High PSRR, Low-Voltage,CMOS Bandgap Reference IC

**broken link removed**
 

cmos ldo psrr design

i am not the member of ieeeclub and can not download the thesis you suggested
 

the membership is free. You just fill up the form to become a club member then you can download everything there for free.
 

you can cut the feedback point,and simulate the psrr of the whole circuit with the 3 subcircuits.
 

suppose your psrr is a total combined effect of your circuit. So you don't need to add all the psrr together (they are not noise power). All you have to do is make sure the signal path from supply to you output. Then run AC for psrr.
 

You can connect the BandGap supply at the LDO output, using a proper wake up circuit. This way the bandgap PSRR is not so critical.
 

you can connect a bypass capacitor at the output of your bandgap voltage externally to reduce psrr caused by bandgap circuitry
 

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