jumbodas
Newbie
Lots of chip have spec for pin voltage limits for example as <Vdd+1V .
let us assume at power up of system a this chip supply is kept off or is slow to rise.
So the other chip sending input to off chip has powered and outputs logic high.
Will it damage the off chip? Will the chip damage depend on how long it is in this state? Will the latchup occur even with fast transient and heat will damage unless chip is reset?
How do then chips tolerate ESD?
I know chips have input protection diode to Vdd so the diode will anyway powerup the off chip but what if there is no diode? What if even with this diode the chip supply is actually tightly pulled by design to keep it off?
Can a current limiting resistor protect the damage even when chip has not specified any current limit that will negate the over voltage limit?
Will this current limit depend on transient duration?
let us assume at power up of system a this chip supply is kept off or is slow to rise.
So the other chip sending input to off chip has powered and outputs logic high.
Will it damage the off chip? Will the chip damage depend on how long it is in this state? Will the latchup occur even with fast transient and heat will damage unless chip is reset?
How do then chips tolerate ESD?
I know chips have input protection diode to Vdd so the diode will anyway powerup the off chip but what if there is no diode? What if even with this diode the chip supply is actually tightly pulled by design to keep it off?
Can a current limiting resistor protect the damage even when chip has not specified any current limit that will negate the over voltage limit?
Will this current limit depend on transient duration?