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# How to calculate required gate resistance

#### Prince Charming

##### Member level 2
I want to limit the rise and fall times of a MOSFET with a gate resistor to prevent large EMI. My calculation is as below:

VDS = 24;
VGS = 12; % driving gate-soruce voltage

Ron = 0.0029; % On resistance at operating point
tr = 30*10^-9; % desired rise time
tf = 30*10^-9; % desired fall time
Qtotal = 17*10^-9; % total gate charge at operating point obtained from datasheet (depends on: VDS, VGS)

Ig = Qtotal/tr % Required Gate Current
Cg = Qtotal/VGS; % Gate capacitance at operating point
RG = tr/(5*Cg)
In this calculation, I thought of a RC circuit at the gate in which the capacitor charges in 5 time constants. I found RG as 4.2ohm. I know this includes internal resistance of the MOSFET too which is not written in the datasheet oddly. Is my thinking correct?

Gate driver: FAN3111ESX

MOSFET: IAUC80N04S6N036ATMA1

Though why a capacitor on the gate?....you can cause gate rise time delay just with a resistor.

...But anyway, if you want the external gate cap, then i think you have to go through the 4 gate time intervals as depicted in the Balogh document and work it out from that......its something like pages 5 to 10 of the Balogh document.......You have to re-work out your gate current for each of the intervals, as it shows.

Laszlo Balogh "High speed mosfet gate drive"

When you are thinking of EMC reasons for this...you are basically speaking of the miller plateau time interval , and slowing that down....because thats when the VDS transistions...which is the causation of the big dv/dt nightmare.......and during the miller plateau interval....the VGS is pretty well constant...so adding a gate cap does nothing to slow that down......its the gate series resistance that slows that down......because it limits the CDS discharge current.

To be honest, at turn OFF, you get most emc benefit by slowing the vds rise up with a turn off snubber (RCD type)....and just smash the VGS down to zero as fast as you can to reduce turn off switching losses.

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Though why a capacitor on the gate?....you can cause gate rise time delay just with a resistor.

...But anyway, if you want the external gate cap,
During voltage rise, the miller capacitance keeps gate voltage about constant.
In case of constant gate voltage the additional capacitance is useless: constant voltage --> zero current --> no effect.

The additional capacitance mainly just causes a delay, but has not much influence on dV/dt.

--> Use the gate resistor only to adjust rise rate.

There are many good application notes available to tell you how to.
Almost any MOSFET manufacturer, almost any driver_IC_manufacturer provides them.

Klaus

Hello, I haven't thought of adding a capacitor to the gate. I considered internal gate capacitance of the mosfet and external gate resistance as RC circuit. So all the C is coming from the existent gate-soruce capacitance + drain-gate capacitance. Is there a formula to calculate gate resistance if I know the required rise time and input capacitance? Maybe I shuld only increase the turn on duration and for turn off, I should bypass gate resistor with a diode and add a RCD snubber to Drain-Soruce.

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The Balogh doc above shows you how to calc the gate resistance.

Basically, for the turn ON...you know Qgd from the datasheet.......so that is the charge that gets used over the interval where vds transitions.
So its i = Qgd/t(miller)

Then you use Ohms Law to calc the series gate resistor...you know the max drive voltage output of the driver, you know the VGS(miller)

So the resistor is gotten by i = [V(DRIVE - VGS(miller)]/R (you worked out i from Qgd/t

Thank you guys, I understood the logic and updated my calculations as below:
%% PWM MOSFET:
f = 1000;
Vi = 24;
VGS = 12; % driving gate-soruce voltage
Vp = 4.7; % plateau voltage
Io_max = 4; %0.78
tr = 30*10^-9; % desired rise time
tf = 15*10^-9; % desired fall time
Qtotal = 17*10^-9; %total gate charge at operating point (VDS, VGS)
Ron = 0.0029; % On resistance at operating point
R_JA = 50; %Junction to Ambient resistance
Vf = 0.5; % Forward voltage drop of the diode on gate at Ig_turnOff

%Turn ON:
Ig_turnOn = Qtotal/tr % Required Gate soruce Current
RG_turnOn = (VGS-Vp)/Ig_turnOn

%Turn OFF:
Ig_turnOff = Qtotal/tf % Required Gate sink Current
RG_turnOff = (Vp-Vf)/Ig_turnOn
Ig_turnOn = 0.5667
RG_turnOn = 12.8824
Ig_turnOff =1.1333
RG_turnOff = 7.4118

Now I'm unsure of the selected rise and fall times. I know that rise time should be slow enough to let flyback diode block the reverse current, in the document it says:
In an optimum design the gate drive speed at turn-on is matched to the diode switching characteristic.
The diode has 8ns Trr thus, I chose 10ns for rise time . For the turn off time the document says the faster the better but of course it also tells us to consider ringing. Since 10ns is pretty fast already I chose the same for fall time. Now the results are:

Ig_turnOn = 1.7A
RG_turnOn = 4.29ohms
Ig_turnOff =1.7A
RG_turnOff = 2.47ohms

which renders my driver insufficient thus, I chose UCC27516DRSR instead. Since the switching frequency is low, the power dissipation on the driver is small that's why I only plan to incorporate parallel 1N4448 diode.

Is 10ns too fast? It will correspond to 100MHz signal plus maybe higher frequency oscillations because of parasitics. Maybe the higher the better because it is far greater than the maximum useful frequency present in the circuit which is 16MHz oscillator of Atmega328p. How should I limit the edge speed? Is making it much greater better than making it for example 60ns which corresponds 16.7MHz which is very close to MCU frequency?

For offline flyback you usually see a VGS rise up in around 50ns or so....but what is you power level?
Remember its the miller bit where the noise is....you can just build it and test, and increase or decrease the gate res to suit.
As the theory is not quite super accurate.

The slowdown of gate edge doesn't happen until the drain
starts to move. So there will be a region of fast gate slew,
(Cgs+Cgd) and driver Ipeak, up to about VT. Then the drain
will move while Miller cap keeps the gate "stuck" and you
see the constant-current drain plateau until drain finishes
its swing, then the gate slew increases again until it hits
the stops.

Gate resistors limit the drain dV/dt but don't entirely keep
the gate dV/dt down. There, look to drive-loop area for EMI
help (though, sure, resistors will help a little if they are
placed at the driver).

But I think you want to know what, gate, drain or both is

I've heard that the rise or fall duration of MOSFET must be longer than resonant period of stray inductance and output capacitance. Output capacitance is given as 326pF in the datasheet. Best thing I can do for stray inductance is to guess, I guessed as 20nH considering the very small packages: gate driver(WSON) gate resistors(0402) MOSFET(PG-TDSON-8). That means T_resonant = 2*pi*sqrt(LstrayCoss) = 16ns. Plus safety, I decided to equate tr=tf=30ns instead of 10ns. There is only a single MOSFET that PWM dims a LED strip and I think that's a pretty simple setup. Sadly I don't have oscilloscope to test but if a problem is faced and it is resolved when I increase gate resistor then I can borrow one.

I am unsure of gate dV/dt part in dicks reply. Most of the input capacitance comes from gate-source capacitance. The gate resistor and gate-source capacitor will reduce dV/dt. But I guess you mentioned about the voltage between the driver and gate resistor. Well, I will place the resistor reallyy close to the driver, would that be good enough?

Also, I know the gate driver and MOSFET must be placed as close as possible but what about the distance between MCU and gate driver? The switch node may be noisy that's why I may want to keep it distant, since PWM signal isn't that fast a moderate distance of few centiemters seems okay maybe? Should I even place a lowpass filter between MCU and gate driver, the low pass filter will let 1kHz PWM signal without causing delays or averaging but it will attenuate 62MHz? Such as 10nF and 1.5kOhms.

Hi,
The gate resistor and gate-source capacitor will reduce dV/dt.
Is it your guessing or does this information come from an application note (or other document). If the latter please post a link to it.

I tend to disagree. .. as already explained in post#3.

***

I personally think tr=tf=10ns is pretty fast, especially since you are talking about 1kHz PWM frequency. Why that fast?

***
Distance between MCU and gate driver:
The title focusses on gate resistance. Here the distance between MCU and driver IC does not matter.

Also you mainly talk about dV/dt. Here also the distance between MCU and driver IC does not matter.

The distance causes delay, causes noise pickup, and for sure needs to be designed for low ringing.
And since we talk about distance: Please mind that all current flows in a loop, not only from A to B.
Thus when you talk about a signal path you also need to consider it´s return path.

In any case: shorter signals are always preferred.

***
Usually GND is the return path and also acts as voltage reference. And especially when (fastly) switching higher current you need to consider the ground bounce, caused by both the DC current and the path´s stray inductance.

Klaus

This is my schematic. And yes I know I don't need to be that fast at switching but I still wanted to learn how to choose rise and fall times. The 30ns fast transients at the drain of MOSFET may cause the meters long LED strip to radiate electromagnetic waves all around the room, maybe for distant applications such as this, one must increase the rise and fall times to 500ns-1us. What do you think?

About grounding, I will pour ground to front and put full ground plane to the back side, I don't think 4 layer is needed but if necessary then the ground plane will be much closer to the signals of course.

About dv/dt, I just said the internal gate-source capacitor and gate-drain capacitor will charge slower because of my external gate resistor, that's why I said dv/dt will decrease.

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If you slow the Tr and Tf characteristics you are trading off EMI versus heat in
MOSFET. Caps and their ESR matter a lot in keeping it out of power leads.
Generally combinations of bulk caps like tants and ceramics best.

Keep gate R close to MOSFET.

Scope probing as you work with proto looking at ground bounce and supply

Regards, Dana.

Hi,

I still wanted to learn how to choose rise and fall times
I recommended to read application notes from semiconductor manufacturers.
They explain what and why and how to drive MOSFETs.

--> If you read some of them ... then refer to the document/chapter/formula of rise and fall times.
Tell us what you do understand and what is unclear.

--> if you did not read any application note ... I guess I´m not the right person for this thread.

*****
1) we don´t know whether you talk about a small device with a single LED in a shielding metal box or you talk about the lighting installation of a huge building.
Thus we can´t give detailed recommendations.
2) you need to fulfill your country´s regulations regarding EMI. We neither know your country nor your application details
3) you are free to choose fast rise/fall ... and keep EMI low by using a HF filter

Klaus

Most of the time I read datasheets of the parts and their application note, you are right, I should read more topic covering application notes. I can't refer to any application note about dv/dt reduction by gate driver, it is all based on my understanding. For the radiation, the LED strip is 5 meters long covering a room. No metal box, even the pcb is in plastic, sorry faraday But I chose 4 layer board for a really low density board to bring return current right under switching currents such: Signal/PWR - GND - GND - Signal/PWR. Cost for single board isn't an issue but my sanity is What kind of HF filter are we talking about and where? Also thanks Dana I've included tantalum caps besides decoupling caps.