[SOLVED] Proportional Integral VHDL code

[sidharth.bolar89]

The simulation results give the output as undefined.
I am not able to understand where I am going with the procedure.
please help

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity p_i is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
fb : in STD_LOGIC_VECTOR (15 downto 0);
pid_o : out STD_LOGIC_VECTOR (31 downto 0));
end p_i;

architecture Behavioral of p_i is

signal temp1,temp2,temp3:std_logic_vector(31 downto 0);
signal p,i,d:std_logic_vector(31 downto 0);
signal set,er,prev: std_logic_vector(15 downto 0);

begin

process (clk, rst)
begin
set<= "0000000000001010";
if rst='0' then pid_o <= "00000000000000000000000000000000";
elsif clk' event and clk = '1' then
er <= set - fb;
p <= "0000000000000011" * er;
i <= i + ("0000000000000010" * er);
--d <= "0000000000000001" * (er - prev);
--prev <= er;
pid_o <= p + i;
end if;

 

[TrickyDicky]

where is your testbench code?

 

[sidharth.bolar89]

I directly created test bench waveform(.tbw file) and the n according to the pattern wizard I applied a up counter to the feedback signal(fb) and simulated it directly using ISE simulator .The output only for P (proportional controller ) gives the expected output but with I(integrator) code included it gives the output as undefined (32xxxxxx)

 

[TrickyDicky]

Well the problem will be that i is never set, so because its an accumulator, it will always be uninitialised.

 

[sidharth.bolar89]

how do i initialize i?...coz i is a 32 bit vector...so how do we declare a constant of type bit_vector?
n it shud b initialized only once i.e at the beginning of the code...after that it shud store the instantaneous values...
we tried declaring a variable prev1 as follows n modified integral part as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity p_i is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
fb : in STD_LOGIC_VECTOR (15 downto 0);
pid_o : out STD_LOGIC_VECTOR (31 downto 0));
end p_i;
PACKAGE tpack IS
CONSTANT prev1:is array(31 downto 0) of bit:="00000000000000000000000000000000";
end tpack;

architecture Behavioral of p_i is

signal temp1,temp2,temp3:std_logic_vector(31 downto 0);
signal prev,p,i,d:std_logic_vector(31 downto 0);
signal set,er: std_logic_vector(15 downto 0);

begin
process(clk,rst)
begin
set<= "0000000000001010";
if rst='0' then pid_o <= "00000000000000000000000000000000";
elsif clk' event and clk = '1' then
er <= set - fb;
p <= "0000000000000011" * er;
i <= prev1 + ("0000000000000010" * er);
--d <= "0000000000000001" * (er - prev);
prev1 <= i;
pid_o <=p+i;
end if;
end process;
end Behavioral;

 

[FvM]

how do i initialize i?...

Strange question. You are initializing pid_o, so it seems like you know how to. Why don't you initialize i?

 

[sidharth.bolar89]

I was getting an error when i tried to initialize it !
Anyways I changed the code The following code is giving me satisfactory results!
Thanks for your help
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pid is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
data_en : in STD_LOGIC;
set_point : in STD_LOGIC_VECTOR (15 downto 0);
fb : in STD_LOGIC_VECTOR (15 downto 0);
pid_o : out STD_LOGIC_VECTOR (31 downto 0));
end pid;

architecture Behavioral of pid is

begin
process(clock) is
variable p,i,der,result: signed(pid_o'range);
begin
if rising_edge(clock) then
if reset = '1' then
i := (others => '0');
der := (others => '0');
elsif data_en = '1' then
p := signed((set_point - fb)* "0000000000000011"); -- data-fb is the error
i := i + signed((set_point-fb) * "0000000000000010");
der := signed((set_point-fb)* "0000000000000001") - der;
result := (p + i + der);
end if;
pid_o <= std_logic_vector(result);
end if;
end process;
end Behavioral;