well I understand that components cannot be instantiated in a process. I don't know if I can explain it better.
The algorithm I am trying to implement uses a while loop and within that loop uses a couple of components mostly division related. While coding with VHDL, I cannot use WHILE loop so I had to replace the WHILE loop with a clock and if statement. However, this doesn;t work as the components cannot be instantiated. This is part of the algorithm that am trying to implement. As you can see within the WHILE loop it uses some components like LSR, MSR which are rather big programs on division. I don't know how to replace the components if I have to replace the while loop with a clocked process~~
while P ≠ 0 do
if [a1a0] = 0 then A = A/4, U = LSR(U,M)
if D < 2 then
if D = 1 then P = P − 1
else P = P − 2
D = D − 2
elsif a0 = 0 then A = A/2, U = MSR (U,M)
if D < 1 then P = P − 1
D = D − 1
else
if ([a1a0] + [b1b0]) mod 4 = 0 then q = 1 else q = −1
if D ¸ 0 then A = (A + qB)/4, U = LSR(U + qV,M)
if D = 0 then P Ã P − 1
D = D − 1
else D = −D − 1, {A = (A + qB)/4, B = A}
{U = LSR(U + qV,M), V = U}