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I can not help you with vhdl description, but may be a genaral notejene2in said:The algorithm I am trying to implement uses a while loop and within
that loop uses a couple of components mostly division related/.../
if [a1a0] = 0 then A = A/4, U = LSR(U,M)
elsif a0 = 0 then A = A/2, U = MSR (U,M)
lsr_out = LSR(x,y); msr_out = MSR(t,z);
/..../
if ( <...> ) U = lsr_out;
else U = msr_out;
as usual - if I understand you correctly ...jene2in said:the next question would be/.../how do I update the inputs