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programming help VHDL

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jene2in

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When I try to map components within a process, all the components are ignored and not recognized.
Is there some way to use components within a process?
 

childs

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What error does it give you? What compiler u using? Can u show the code? :)
 

jene2in

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well I understand that components cannot be instantiated in a process. I don't know if I can explain it better.

The algorithm I am trying to implement uses a while loop and within that loop uses a couple of components mostly division related. While coding with VHDL, I cannot use WHILE loop so I had to replace the WHILE loop with a clock and if statement. However, this doesn;t work as the components cannot be instantiated. This is part of the algorithm that am trying to implement. As you can see within the WHILE loop it uses some components like LSR, MSR which are rather big programs on division. I don't know how to replace the components if I have to replace the while loop with a clocked process~~

while P ≠ 0 do
if [a1a0] = 0 then A = A/4, U = LSR(U,M)
if D < 2 then
if D = 1 then P = P − 1
else P = P − 2
D = D − 2
elsif a0 = 0 then A = A/2, U = MSR (U,M)
if D < 1 then P = P − 1
D = D − 1
else
if ([a1a0] + [b1b0]) mod 4 = 0 then q = 1 else q = −1
if D ¸ 0 then A = (A + qB)/4, U = LSR(U + qV,M)
if D = 0 then P Ã P − 1
D = D − 1
else D = −D − 1, {A = (A + qB)/4, B = A}
{U = LSR(U + qV,M), V = U}
 

j_andr

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jene2in said:
The algorithm I am trying to implement uses a while loop and within
that loop uses a couple of components mostly division related/.../
I can not help you with vhdl description, but may be a genaral note
about hardware will be useful:
you have to instantiate all your computing unit 'unconditionaly'
and in "IF's" switch their inputs and/or outputs;
just as an illustrative example:
Code:
if [a1a0] = 0 then A = A/4, U = LSR(U,M) 
elsif a0 = 0 then A = A/2, U = MSR (U,M)
you need both units LSR and MSR implemented and in an
IF statemen choose what value is connected to U register;
something like:
Code:
   lsr_out = LSR(x,y);   msr_out = MSR(t,z);
 /..../
   if ( <...> ) U = lsr_out;
   else         U = msr_out;
the same relates to inputs of a unit;
---
 

jene2in

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Thanks for your reply. It makes sense. I guess the next question would be the components are to be used in every loop till the condition is met and everytime the inputs to the components are updated from the previous loop, how do I update the inputs.

According to my knowledge your suggestion helps if there is just one iteration, but in the algorithm the components are used every loop with updated inputs. May be am missing something here!!!!!!!!!!

Thanks.
 

j_andr

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jene2in said:
the next question would be/.../how do I update the inputs
as usual - if I understand you correctly ...

< unit instantiation >
< signal unit_output declaration >

< process statement >
if/while < some conditions >
unit_output = unit(x,y);
else
unit_output = unit_output;
< end process >

<probably clocked process>
x [or y] = unit_output;
---
 

avimit

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You can use vhdl functions insead of components, and then you can use those functions just like they are used in alogirhtm.
for example if a vhdl function is called MAX or MIN, then you can use these inside a process;

signal_a <= MAX(signal_b, signal_c, signal_d, signal_e)
 

jene2in

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I will think about the reply by j_andr. Will try to work on it and see if this is wghat can be done.

ABout the functions, I can convert the components to functions but as I mentioned earlier my components are rather big programs with divider, adder components in it. So I am not sure if I can convert my components to functions as the components have other components within it.

I know it's rather confusing.
Thanks for all your replies.
 

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