Let me clearfy this, I inherited a board (SPARTAN-6) that it's designer forgat to fanout the configure flash pinout.
(no access to the balls on the BGA) - so for bybass that issue each time powers up the uC configre that FPGA
Surely possible. Altera provided a "Jrunner" code for the same purpose. Besides handling JTAG (almost easy) you need to understand the JTAG configuration load algorithm used by your FPGA. It should be documented somewhere.
Alera devices (and Xilinx would be similar) have "passive configuration" capability in which an external device shall configure the FPGA. On development boards this often ends up being a MAX II or MAX V CPLD. Read about passive configuration. A microcontroller could also be used here, it shall just read data from external configuration memory and write to the FPGA.