vani_pat
Junior Member level 1
Hi All,
I have written vhdl code for input clock freq scaling from 32 MHz down to 8 MHz as follows:
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY timeInterval_reg IS
GENERIC(REGWIDTH : integer := 2);
PORT( clk_out : OUT std_logic;
----This factor is equal to 125ns/31.25ns = 4 to achieve 8 MHz(125ns)--------
clk_period : IN std_logic_vector(REGWIDTH-1 downto 0):= "11";
en : IN std_logic:= '1';
clk : IN std_logic);
rst_n : IN std_logic;
end entity timeInterval_reg;
architecture rtl of timeInterval_reg is
signal wrap : std_logic:= '0';
signal count : std_logic_vector(REGWIDTH-1 downto 0):= (OTHERS => '0');
begin
process (clk, en, wrap)
begin
if (rst_n = '0') then
count <= '0';
wrap <= '0';
if rising_edge(clk) then
if (en = '1') then
if (count = clk_period) then
wrap<='1';
count <= (OTHERS => '0');
else
wrap <= '0';
count <= count+1;
end if;
else
wrap <= '0';
end if;
end if;
end if;
end if;
end process;
clk_out <= wrap;
end rtl;
I have tested it on the ISIM using test bench it works fine, but as I programmed it to my fpga board and checked through scope no response has been displayed corresponding to clk_out signal, it shows zero signal. I am using Papilio one fpga board and has set proper pin connections to ucf file. Is my code is logically correct?? or I am missing any requirement needed.
Thanx in advance!!!
I have written vhdl code for input clock freq scaling from 32 MHz down to 8 MHz as follows:
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY timeInterval_reg IS
GENERIC(REGWIDTH : integer := 2);
PORT( clk_out : OUT std_logic;
----This factor is equal to 125ns/31.25ns = 4 to achieve 8 MHz(125ns)--------
clk_period : IN std_logic_vector(REGWIDTH-1 downto 0):= "11";
en : IN std_logic:= '1';
clk : IN std_logic);
rst_n : IN std_logic;
end entity timeInterval_reg;
architecture rtl of timeInterval_reg is
signal wrap : std_logic:= '0';
signal count : std_logic_vector(REGWIDTH-1 downto 0):= (OTHERS => '0');
begin
process (clk, en, wrap)
begin
if (rst_n = '0') then
count <= '0';
wrap <= '0';
if rising_edge(clk) then
if (en = '1') then
if (count = clk_period) then
wrap<='1';
count <= (OTHERS => '0');
else
wrap <= '0';
count <= count+1;
end if;
else
wrap <= '0';
end if;
end if;
end if;
end if;
end process;
clk_out <= wrap;
end rtl;
I have tested it on the ISIM using test bench it works fine, but as I programmed it to my fpga board and checked through scope no response has been displayed corresponding to clk_out signal, it shows zero signal. I am using Papilio one fpga board and has set proper pin connections to ucf file. Is my code is logically correct?? or I am missing any requirement needed.
Thanx in advance!!!