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Dimensions of wires and Vias changes. Hence parasitic Resistance and Capacitance change too leading to an unbalanced circuit because of data signal delay and clock skew. Power consumption will differt also and gradient of temperature can be observed in different location of the wires.
Typically increases the delay, specially in long lines. You can find the data related to the values of interconnect resistors and capacitors in the design kit which typically provided by foundry ( like RCTYP, RCMAX, .....). If you are designing high speed VLSI circuit, it is mandatory to take into account the effect of interconnect in your schematic( very roughly.)