Hey @dick_freebird,
thanks for the answer, that really helped.
I've got a question about each model (UP, DOWN, FAST, and SLOW) I've been simulating each of them (eg. replacing all typical models with fast models, etc...) to see whether the circuit is still 'acceptable'. UP model seems to have degraded the gain of my buffer quite much (>0.95). Is this because of the variations in threshold voltage?
I'm actually not quite sure what each model does at all, would you be able to point me to any textbooks or articles?, I'm currently using [CMOS Circuit Design Layout and Simulation 3rd Ed]