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[SOLVED] process variation and matching?

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flabbergastt

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Hi,

I've been simulating a 2-stage op-amp using MOSFETs. These MOSFET models come with (typical, fast, slow, up and down).

I've only done simulations using typical models and am not sure how the rest of the MOSFET variation works.

Do I simply replace all the typical values (the op-amp works well with typical models) with each variation and see the extreme corners?

I am not familiar with process variations at all but would like to know the best approach. I'm currently using LTSpice and would like to get the most out of it.

Any help is appreciated, thanks!
 

dick_freebird

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Generally you'd get corner models as parallel hierarchies or
chains of model & parameter files, invoking one of them at
a time. If you have the right command language you might
even be able to loop through corners.

Mismatch is entirely another matter. You need things like
VT to have statistics, and the simulator preprocessing to
create model-per-device or the simulator core to support
the parameter dispersion internal to the compact model
somehow.

To poor-boy it, you could put your FET inside a wrapper
(subcircuit) with a DC voltage source inseries with the gate
with a gauss() argument that gives you a technology-
appropriate VT distribution (to do really right, this distribution
would be L and W dependent following observed matching vs
area relation, which you might be able to do (again depending
on the simulator's language qualities) from the subcircuit
call's parameters.
 

flabbergastt

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Hey @dick_freebird,

thanks for the answer, that really helped.
I've got a question about each model (UP, DOWN, FAST, and SLOW) I've been simulating each of them (eg. replacing all typical models with fast models, etc...) to see whether the circuit is still 'acceptable'. UP model seems to have degraded the gain of my buffer quite much (>0.95). Is this because of the variations in threshold voltage?

I'm actually not quite sure what each model does at all, would you be able to point me to any textbooks or articles?, I'm currently using [CMOS Circuit Design Layout and Simulation 3rd Ed]
 

erikl

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flabbergastt

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Hey @erikl

Thanks for the model file, that makes it really clear.
I've got one question. I've read that there are many ways to analyze process variation, corner analysis, interval analysis, monte carlo, etc.
Since corner analysis invokes the 'worst corners', does this mean its the most accurate way to analyze process variation?

Thanks!
 

erikl

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Since corner analysis invokes the 'worst corners', does this mean its the most accurate way to analyze process variation?
Let's say corner analysis should involve the first analyses after your typical one. You are responsible to choose the right V & T limits (for the application) together with the corresponding P 'worst corners' (usually minimum V & highest T for SS P, and vice versa for FF P).

It's a good start if your circuit works well at all typical and corner conditions, but it doesn't secure that it will work well at all possible condition combinations (I remember the case where our circuit was ok at all corners (even at -55°C), but its oscillator didn't start at min. V and -25°C).

And why? Corner analysis doesn't consider condition combinations between the limits (that's what its name tells), and it doesn't consider mismatch, which is vitally essential at least in high-resolution analog circuits. For this you need Monte Carlo analysis with the associated MC process & mismatch variation parameters to be provided by the foundry. This allows to find "runaway" combinations and even can provide a yield forecast for high volume production on a statistical base.
 

flabbergastt

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Hey @erikl

It's really clear to me now. I'm assuming the mismatch variation parameters are "Avt and Ab"? for threshold and current factor. I am using LTSpice. From what I've seen, mismatch can be analyzed using LTSpice. How would I go about doing this?

Thanks!
 

erikl

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I'm assuming the mismatch variation parameters are "Avt and Ab"? for threshold and current factor.
Right. Aβ summarizes the mismatch from Cox, µ0, W & L , s. e.g. "Matching Properties of MOS Transistors" by Pelgrom et. al. Here you can find some values from different process sizes.


I am using LTSpice. From what I've seen, mismatch can be analyzed using LTSpice. How would I go about doing this?
I'm not familiar with LTSpice, sorry.
 

Mvar

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Hey @erikl

Thanks for all the help!, I used @dick_freebird method for mismatch using LTSpice and it has some decent results.
 

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