process statement and generate statement in vhdl

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity unsigned_exponent_adder is
    Port ( a, b : in  STD_LOGIC_VECTOR (07 downto 0);
                clk :in std_logic;
 
           sumo : out  STD_LOGIC_VECTOR (08 downto 0));
end unsigned_exponent_adder;
 
architecture Behavioral of unsigned_exponent_adder is
 
 
component half_add is
       Port ( a,b : in  STD_LOGIC;
     clk: in std_logic;
           s, c : out  STD_LOGIC);
end component;
 
component full_adder is
    Port ( a, b,clk, cin : in  STD_LOGIC;
           cout, sum : out  STD_LOGIC);
end component;
SIGNAL carryv: STD_LOGIC_VECTOR(8 DOWNTO 1);
 
 
begin
process(clk)
begin
IF clk'EVENT AND clk = '1' THEN
 
halfadder: half_add port map (a(0), b(0),clk,sumo(0) ,carryv(1) );
 
adder: FOR k IN 7 DOWNTO 1 GENERATE
FullAdder: full_adder PORT MAP (a(k), b(k),clk, carryv(k), Carryv(k+1), sumo(k));
END GENERATE adder;
sumo(8)<= carryv(8);
 
END IF;
end process;
 
end Behavioral;