EceWoman
Newbie level 3
Hello! I'm new in VHDL programming and I have a problem understanding sensitivity list. So, I was trying to solve an exercise (9.14 from Frank Vahid's book) and tried to implement the FSM in the picture. I wrote the following that didn't work - I won't copy the whole code but the specific part:
(1st wrong solution with 1 process)
then, after searching at book I found these two solutions that actually work :
(2nd solution with 2 processes)
and
(3rd solution with only 1 process)
I would be glad if you could answer my questions :
1 - why my suggested solution didn't work ? if I use 2 processes do I have to include all signals in the second sensitivity list? ( "process(all)")
2 - if I insert all input signals in the sensitivity list is there any possibility for failure ? for example , if state signal remains stable, but call signal (input) changes in the second process?
3 - in the case of using 2 processes, the hold/setup times for example of the state signal doesn't affect us ?
Thank you for your time!
(1st wrong solution with 1 process)
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 process(clk) begin if(clk='1' and clk'event) then if(reset='1') then state <= liOFF ; else state <= nextState; end if; end if; end process; -- combinational logic process(state) begin case state is when liOFF => l <='0'; if (call = '1') then nextState <= liON; else nextState <= liOFF; end if;
then, after searching at book I found these two solutions that actually work :
(2nd solution with 2 processes)
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 process(clk) begin if(clk='1' and clk'event) then if(reset='1') then state <= liOFF ; else state <= nextState; -- gia 0 ns ? end if; end if; end process; -- combinational logic process(state,call,cncl) -- state and 2 input signals in sensitivity list begin case state is when liOFF => l <='0'; if (call = '1') then nextState <= liON; else nextState <= liOFF; end if;
and
(3rd solution with only 1 process)
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 process(clk) -- one process with only clk in the sensitivity list begin if(clk='1' and clk'event) then if(reset='1') then state <= liOFF ; else state <= nextState; -- gia 0 ns ? end if; end if; -- combinational logic case state is when liOFF => l <='0'; if (call = '1') then nextState <= liON; else nextState <= liOFF; end if; end process;
I would be glad if you could answer my questions :
1 - why my suggested solution didn't work ? if I use 2 processes do I have to include all signals in the second sensitivity list? ( "process(all)")
2 - if I insert all input signals in the sensitivity list is there any possibility for failure ? for example , if state signal remains stable, but call signal (input) changes in the second process?
3 - in the case of using 2 processes, the hold/setup times for example of the state signal doesn't affect us ?
Thank you for your time!
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