Process corner simulation

[rocky.king07]

I am designing an ADC. Process file containing 5 corners. TT, FF, SS, SF and FS. To simulate the ADC, is it required to choose every process corner? According to process document SF and FS corner is having 5 sigma variation w.r.t. to TT corner and FF and SS corner are having 3 sigma variation w.r.t TT corner. If I have simulated ADC with TT, FF, SF and FS corners, is it fine? How much probability is there to come SS corner with fabricated lot?

 

[erikl]

If I have simulated ADC with TT, FF, SF and FS corners, is it fine?

It is fine, if all sim. runs provided good results. But also the SS corner run must provide a good result.

How much probability is there to come SS corner with fabricated lot?

This question can only be answered by your foundry/fab, I think.

 

[Ziqi]

if your circuit had CAP or RES, 9 times corners should be simulated. power supply and temperature corners are always considered in analog circuits. simulation times increase exponentially, that may torment you.
but a designer is not a worker just to run simulator, it would be better to know which is the worst corner for which circuit parameter. for example, corner "ss, cap_ss" may the worst corner for settling time, however corner "ff, cap_ff" may the worst for stability. optimize every single design parameter to meet the corresponding worst corner, and make trade-off between them.

 

[Junus2012]

Run all the corner to have all the possibilities of the worst case.

 

[dick_freebird]

These corners are "digital" and may or may not apply the actual
worst case condition for an analog circuit. So you should check
them all, yet not believe they've shown you everything that
matters.

Now depending on how sophisticated your foundry modeling
team is (or how much of that, they chose to push into an
external PDK) your "slow, slow" corner could be:

- A dumb, WAT-limit-based and unrealistic corner (some
elements are co-variant, some are anti-)

or

- a "slowest realistic P for slowest WAT+guardband N"
type of scheme, and maybe its complement. This is
less design overkill, but requires more analysis of the
process historical scatter-map, which on nodes early
in their production life, isn't always consistent or
complete enough.

 

[rocky.king07]

I am not interested in 100% yield. Corner simulation shows deviation w.r.t. typical (the corner for which process is optimized). If SS corner is having 5 sigma variation w.r.t TT then possibility of occurrence of this corner in any wafer or any die is very less. So expected yield loss will be very less due to SS corner, if process is not having any drastic drift. Please make me correct if any statement is wrong.

 

[dick_freebird]

That's all true, but in the real world there are competing
interests and some of them will hold up your tape-out if
you can't convince them this isn't a lot-level yield bust
waiting to happen.

If you have the authority, then you can go for it on
whatever basis you like.

 

[tzg6sa]

The main point behind simulating all corners is to pinpoint critical circumstances for the circuits. With other words: if your circuit passes all the extreme corners then people will be more confident that it will work.

 

[micpro]

If SS corner is having 5 sigma variation w.r.t TT then possibility of occurrence of this corner in any wafer or any die is very less. So expected yield loss will be very less due to SS corner, if process is not having any drastic drift. Please make me correct if any statement is wrong.

It's not entirely correct ... I'd say you're right that if your circuit works at the SS corner in simulation, then you don't expect a yield loss if the process drifts exactly into that direction.
However, the way how SS/FF/SF/FS corners vary device parameters do not show the complete picture of all possible device variation, but only those relevant to digital gates (Ion and Vth). Whereas analog performances depending on small signal parameters (gm, rds, Cgs, ...) often vary wider than what corner simulation shows.
For example, the 3-sigma variation of gain and phase margin of OTAs inside the ADC may by much wider than what the 5-sigma SS/FF/FS/SF corner simulation shows to you. Process MC runs may therefore show a significant yield loss for analog specs even if they are fine at all corners.