These corners are "digital" and may or may not apply the actual
worst case condition for an analog circuit. So you should check
them all, yet not believe they've shown you everything that
matters.
Now depending on how sophisticated your foundry modeling
team is (or how much of that, they chose to push into an
external PDK) your "slow, slow" corner could be:
- A dumb, WAT-limit-based and unrealistic corner (some
elements are co-variant, some are anti-)
or
- a "slowest realistic P for slowest WAT+guardband N"
type of scheme, and maybe its complement. This is
less design overkill, but requires more analysis of the
process historical scatter-map, which on nodes early
in their production life, isn't always consistent or
complete enough.