cosmonutt
Newbie level 6
hi
how do i go about synthesizing a fairly big design in parts.
i have synthesized the sub modules that have a number of rtl files each.
now when synthesizing the top level file, i am reading the synthesized verilog netlists and the top level .v file. however this is not working. what all do i need to read in??? to synthesize at the top level and join all the small modules??
how do i go about synthesizing a fairly big design in parts.
i have synthesized the sub modules that have a number of rtl files each.
now when synthesizing the top level file, i am reading the synthesized verilog netlists and the top level .v file. however this is not working. what all do i need to read in??? to synthesize at the top level and join all the small modules??