Procedure for synthesizing large designs in DC

[cosmonutt]

hi

how do i go about synthesizing a fairly big design in parts.
i have synthesized the sub modules that have a number of rtl files each.
now when synthesizing the top level file, i am reading the synthesized verilog netlists and the top level .v file. however this is not working. what all do i need to read in??? to synthesize at the top level and join all the small modules??

 

[AdvaRes]

Re: regarding synthesis

hi

how do i go about synthesizing a fairly big design in parts.
i have synthesized the sub modules that have a number of rtl files each.
now when synthesizing the top level file, i am reading the synthesized verilog netlists and the top level .v file. however this is not working. what all do i need to read in??? to synthesize at the top level and join all the small modules??

I dont know what tool are you using for synthesis but this is the general procedure.
Create a project and add all the .v files. Then compile.
Note that some tools require to sort theses files by order according to their hierarchy.

 

[sree205]

regarding synthesis

if you are using design compiler, read all the files together and set the current design to the top level module and then link. during linking, it should read in all the instances of the files and then link them to the previous files compiled. hopefully, this should work

 

[cosmonutt]

Re: regarding synthesis

thanks tons.

but its still not completely clear.
i am using dc. so i should read in the synthesized netlists and the non- synthesized top level file . and then link them .. and go ahead with the normal synthesis..(do i need to read in the rtl of the modules that i have already synthesized?? ).
could you suggest some good book on all aspects of dc?

 

[ljxpjpjljx]

Re: regarding synthesis

you have done the synthesis of the sub module in DDC format ,then read all this files and do the top level synthesis!

 

[avimit]

regarding synthesis

There are 2 approaches
1). top-down,
2). bottom-up
What you are doing here is essentially bottom-up, which in my opinion is the right way to go for large designs. In this case usually, all the sub-modules are synthesized and saved as 'ddc' rather than verilog netlists. You can save verilog netlists as well, but then the verilog netlist will not preserve 'constraints' you have at the time of synthesizing the sub modules.
Once you have saved the ddcs for the sub-modules, you then read in the top level, and then read in the ddcs of all sub-modules. You do NOT have to read the RTL for sub modules. You may want to put 'dont touch' attribute on sub modules, if you do not want to distrub them.

While in top-down approach, you dont synthesize the sub-modules and read-in all the RTL i.e top level RTL and sub-modules RTL in once, and then synthesize it.
Hope it helps,
Kr,
Avi