regarding synthesis
There are 2 approaches
1). top-down,
2). bottom-up
What you are doing here is essentially bottom-up, which in my opinion is the right way to go for large designs. In this case usually, all the sub-modules are synthesized and saved as 'ddc' rather than verilog netlists. You can save verilog netlists as well, but then the verilog netlist will not preserve 'constraints' you have at the time of synthesizing the sub modules.
Once you have saved the ddcs for the sub-modules, you then read in the top level, and then read in the ddcs of all sub-modules. You do NOT have to read the RTL for sub modules. You may want to put 'dont touch' attribute on sub modules, if you do not want to distrub them.
While in top-down approach, you dont synthesize the sub-modules and read-in all the RTL i.e top level RTL and sub-modules RTL in once, and then synthesize it.
Hope it helps,
Kr,
Avi