pakha
Newbie level 4
Hi,
I am trying to write verilog code for 4:1 mux using rtl but I am finding difficulty in the test bench code. please correct me
The code goes as follows
I am trying to write verilog code for 4:1 mux using rtl but I am finding difficulty in the test bench code. please correct me
The code goes as follows
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 module multiplexer(a,b,c,d,s,out); input a,b,c,d; input[1:0]s; output y; reg y; always@(a or b or c or d or s) begin if(s==2'b00) y=a; elseif(s==2'b01) y=b; elseif(sel==2'b10) y=c; else y=d; end endmodule Test bench module tmux; wire y; reg a,b,c,d; reg s0,s1; mux4 mux(.y(y),.a(a),.b(b),.c(c),.d(d),.s0(s0),.s1(s1)); initial begin s=0, a=0,b=0,c=0,d=0; #10a=2'b11; #10b=2'b11; #10c=2'b11; #10d=2'b11; #10sel=2'b11; end endmodule;
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