parameter buswidth = 32;
parameter busdepth = 128;
module FIFO(
input [buswidth-1:0] Data_In,
output reg [buswidth-1:0] Data_Out,
output reg Empty,
output reg Full,
input Store, //pulse high to store whatever is at Data_In
input Read, //pulse high to clear whatever is at Data_Out
input Reset,
input Clock
);
reg [buswidth - 1:0] FIFOMemory [busdepth - 1:0];
reg [7:0] Top;
reg [7:0] Bottom;
reg [7:0] ValuesStored;
reg OldStore, OldRead;
always @(posedge Clock)
begin
if (Reset)
begin
Top = 0; //where to write to next
Bottom = 0; //where you're currently reading from
ValuesStored = 0;
OldStore = 0;
OldRead = 0;
end
else if (OldRead == 0 && Read == 1)
begin
if (ValuesStored != 0)
begin
if (Bottom == 0) Bottom <= busdepth - 1;
else Bottom <= Bottom - 1;
ValuesStored <= ValuesStored - 1;
end
OldRead = Read;
end
else if (OldStore == 0 && Store == 1)
begin
if (ValuesStored != busdepth - 1)
begin
FIFOMemory[Top] = Data_In;
if (Top == busdepth - 1) Top <= 0;
else Top <= Top + 1;
end
OldStore = Store;
end
else
begin
OldRead = Read;
OldStore = Store;
end
end
always
begin
if (ValuesStored == 0)
begin
Empty = 1;
Full = 0;
Data_Out = 0;
end
else if (ValuesStored == busdepth)
begin
Empty = 0;
Full = 1;
Data_Out = FIFOMemory[Bottom];
end
else
begin
Data_Out = FIFOMemory[Bottom];
end
end;
endmodule