Problems with verilog FIFO implemented with ISE Webpack (ISim locks up - I think)

[uoficowboy]

Hi - I am very new to Verilog and am just learning the basics. I am trying to implement a slightly strange FIFO. I finished coding it, and created a test fixture for it. I tried simulating the test fixture in ISim and nothing seems to happen - I believe ISim is locking up. I have other simulations that run just fine - but this one just won't run. See below for my code, test fixture, and console logs from both ISE and ISim. Apologies for not better commenting the code - I normally comment once things are working... and this so far isn't!!

parameter buswidth = 32;
parameter busdepth = 128;

module FIFO(
    input [buswidth-1:0] Data_In,
    output reg [buswidth-1:0] Data_Out,
    output reg Empty,
    output reg Full,
    input Store, //pulse high to store whatever is at Data_In
	 input Read, //pulse high to clear whatever is at Data_Out
	 input Reset,
	 input Clock
    );

	reg [buswidth - 1:0] FIFOMemory [busdepth - 1:0];
	reg [7:0] Top;
	reg [7:0] Bottom;
	reg [7:0] ValuesStored;
	reg OldStore, OldRead;
	
	always @(posedge Clock)
	begin
		if (Reset)
		begin
			Top = 0; //where to write to next
			Bottom = 0; //where you're currently reading from
			ValuesStored = 0;
			OldStore = 0;
			OldRead = 0;
		end
		else if (OldRead == 0 && Read == 1)
		begin
			if (ValuesStored != 0)
			begin
				if (Bottom == 0) Bottom <= busdepth - 1;
				else Bottom <= Bottom - 1;
				ValuesStored <= ValuesStored - 1;
			end
			OldRead = Read;
		end
		else if (OldStore == 0 && Store == 1)
		begin
			if (ValuesStored != busdepth - 1)
			begin
				FIFOMemory[Top] = Data_In;
				if (Top == busdepth - 1) Top <= 0;
				else Top <= Top + 1;
			end
			OldStore = Store;
		end
		else
		begin
			OldRead = Read;
			OldStore = Store;
		end
	end
	
	always
	begin
		if (ValuesStored == 0)
		begin
			Empty = 1;
			Full = 0;
			Data_Out = 0;
		end
		else if (ValuesStored == busdepth)
		begin
			Empty = 0;
			Full = 1;
			Data_Out = FIFOMemory[Bottom];
		end
		else
		begin
			Data_Out = FIFOMemory[Bottom];
		end
	end;

endmodule

And the test fixture:

module FIFO_TF;

	// Inputs
	reg [31:0] Data_In;
   reg Store;
   reg Read;
   reg Reset;
   reg Clock;

	// Outputs
	wire [31:0] Data_Out;
	wire Empty;
	wire Full;

	// Instantiate the Unit Under Test (UUT)
	FIFO uut (
		.Data_In(Data_In), 
		.Store(Store), 
		.Read(Read), 
		.Reset(Reset), 
		.Clock(Clock), 
		.Data_Out(Data_Out),
		.Empty(Empty),
		.Full(Full)
	);

	initial begin
		// Initialize Inputs
		Data_In = 32'hAAEEAAEE;
		Store = 0;
		Read = 0;
		Reset = 1;
		// Wait 100 ns for global reset to finish
		#50;
		Reset = 0;
		#50
		
		Store = 1;
		#50
		Store = 0;
		Data_In = 2;
		
		Store = 1;
		#50
		Store = 0;
		Data_In = 3;
		
		Store = 1;
		#50
		Store = 0;
		Data_In = 4;
		
		Store = 1;
		#50
		Store = 0;
		Data_In = 5;
		
		Store = 1;
		#50
		Store = 0;
		Data_In = 6;
		

	end
	always
	begin
		Clock = 0;
		#25;
		Clock = 1;
		#25;
	end
endmodule

here is ISE's output:

Started : "Simulate Behavioral Model".

Determining files marked for global include in the design...
Running fuse...
Command Line: fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o C:/HDL/tutorial1/FIFO_TF_isim_beh.exe -prj C:/HDL/tutorial1/FIFO_TF_beh.prj work.FIFO_TF work.glbl {}
Running: C:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o C:/HDL/tutorial1/FIFO_TF_isim_beh.exe -prj C:/HDL/tutorial1/FIFO_TF_beh.prj work.FIFO_TF work.glbl 
ISim P.49d (signature 0x7708f090)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Analyzing Verilog file "C:/HDL/tutorial1/FIFO.v" into library work
WARNING:HDLCompiler:1591 - "C:/HDL/tutorial1/FIFO.v" Line 22: Root scope declaration is not allowed in verilog 95/2K mode
WARNING:HDLCompiler:1591 - "C:/HDL/tutorial1/FIFO.v" Line 23: Root scope declaration is not allowed in verilog 95/2K mode
Analyzing Verilog file "C:/HDL/tutorial1/FIFO_TF.v" into library work
Analyzing Verilog file "C:/Xilinx/14.4/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Compiling module FIFO
Compiling module FIFO_TF
Compiling module glbl
Time Resolution for simulation is 1ps.
Compiled 3 Verilog Units
Built simulation executable C:/HDL/tutorial1/FIFO_TF_isim_beh.exe
Fuse Memory Usage: 27420 KB
Fuse CPU Usage: 451 ms
Launching ISim simulation engine GUI...
"C:/HDL/tutorial1/FIFO_TF_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd  -wdb "C:/HDL/tutorial1/FIFO_TF_isim_beh.wdb"
ISim simulation engine GUI launched successfully

Process "Simulate Behavioral Model" completed successfully

Started : "Launching ISE Text Editor to edit FIFO_TF.v".

And what little ISIM says:

ISim P.49d (signature 0x7708f090)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
Simulator is doing circuit initialization process.

Normally, when ISim is working, it goes on to say:

Finished circuit initialization process.
ISim>