Problems with skip clock in a pll design

[kinysh]

pll skip clock

we are using a pll on chip.
input 12M, output 96Mhz, we divide it by 4 and output to the pad,

when we monitor the pad,
sometimes the logic analyzier will display a min frequcecy of 12Mhz.
it takes about 1-2 minutes.

how could this happen in a pll design.

 

[flatulent]

instrumentation problem?

It could be an instrumentation problem caused by your logic analyzer. Try examining the pad with a digital storage scope and look for unexpected voltage levels and pulse widths. The newer Tektronix scopes can be set to trigger on undersized or oversized pulses.

 

[kinysh]

yes, I also doubt that, I will try it figure that out tomorrow.

but what strange is at measure a 45Mhz output is better than a 22.5Mhz.
I monitore 45Mhz severial minutes, not problem.
22.5Mhz will have probelm easily in the same period.

bests
kinysh

 

[Nobody]

some AMP gain in your circuit get too high in low frequency range and result in spurious oscilation .

 

[kinysh]

Thanks, all
the stupid scope make the mistake.

but after that, I still find some bit pll jitter, about >1 ns

bests
qysheng